GTA04 U-Boot

GTA04 U-Boot Commit Details

Date:2003-03-06 01:58:30 (10 years 2 months ago)
Author:wdenk
Branch:gta04
Commit:db2f721ffcf9693086a7e5c6c7015f2019e7f52e
Parents: 43d9616cffb4a130e1620e3e33fc9bc1bcabe399
Message:* Patch by Rune Torgersen, 13 Feb 2003: Add support for Motorola MPC8266ADS board

* Patch by Kyle Harris, 19 Feb 2003:
patches for the Intel lubbock board:
memsetup.S - general cleanup (based on Robert's csb226 code)
flash.c - overhaul, actually works now
lubbock.c - fix init funcs to return proper value

* Patch by Kenneth Johansson, 26 Feb 2003:
- Fixed off by one in RFTA calculation.
- No need to abort when LDF is lower than we can program it's only
minimum timing so clamp it to what we can do.
- Takes function pointer to function for reading the spd_nvram. Usefull
for faking data or hardcode a module without the nvram.
- fix other user for above change
- fix some comments.

* Patches by Brian Waite, 26 Feb 2003:
- fix port for evb64260 board
- fix PCI for evb64260 board
- fix PCI scan

* Patch by Reinhard Meyer, 1 Mar 2003:
Add support for EMK TOP860 Module

* Patch by Yuli Barcohen, 02 Mar 2003:
Add SPD EEPROM support for MPC8260ADS board
Changes:
Cboard/RPXlite/Makefile → board/emk/top860/Makefile
Cboard/mbx8xx/u-boot.lds → board/emk/top860/u-boot.lds
Cboard/fads/u-boot.lds.debug → board/emk/top860/u-boot.lds.debug
Cboard/mpc8260ads/Makefile → board/mpc8266ads/Makefile
Cboard/mpc8260ads/config.mk → board/mpc8266ads/config.mk
Cboard/mpc8260ads/flash.c → board/mpc8266ads/flash.c
Cboard/mpc8260ads/mpc8260ads.c → board/mpc8266ads/mpc8266ads.c
Cboard/iphase4539/u-boot.lds → board/mpc8266ads/u-boot.lds
Cinclude/configs/MPC8260ADS.h → include/configs/MPC8266ADS.h
Aboard/emk/top860/flash.c (full)
Aboard/emk/top860/top860.c (full)
Ainclude/configs/TOP860.h (full)
Ainclude/spd.h (full)
Ainclude/spd_sdram.h (full)
MCHANGELOG (1 diff)
MCREDITS (2 diffs)
MMAINTAINERS (3 diffs)
MMAKEALL (2 diffs)
MMakefile (2 diffs)
Mboard/ebony/ebony.c (2 diffs)
Mboard/evb64260/evb64260.c (1 diff)
Mboard/evb64260/pci.c (6 diffs)
Mboard/lubbock/config.mk (1 diff)
Mboard/lubbock/flash.c (5 diffs)
Mboard/lubbock/lubbock.c (2 diffs)
Mboard/lubbock/memsetup.S (3 diffs)
Mboard/mpc8260ads/mpc8260ads.c (4 diffs)
Mboard/w7o/init.S (1 diff)
Mboard/walnut405/walnut405.c (2 diffs)
Mcpu/ppc4xx/spd_sdram.c (13 diffs)
Mdrivers/pci_auto.c (1 diff)
Minclude/configs/MPC8260ADS.h (1 diff)
Minclude/configs/W7OLMC.h (1 diff)
Minclude/configs/W7OLMG.h (1 diff)
Minclude/configs/lubbock.h (5 diffs)

File differences

CHANGELOG
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Changes since U-Boot 0.2.2:␊
======================================================================␊
␊
* Patch by Rune Torgersen, 13 Feb 2003:␊
Add support for Motorola MPC8266ADS board␊
␊
* Patch by Kyle Harris, 19 Feb 2003:␊
patches for the Intel lubbock board:␊
memsetup.S - general cleanup (based on Robert's csb226 code)␊
flash.c - overhaul, actually works now␊
lubbock.c - fix init funcs to return proper value␊
␊
* Patch by Kenneth Johansson, 26 Feb 2003:␊
- Fixed off by one in RFTA calculation. ␊
- No need to abort when LDF is lower than we can program it's only␊
minimum timing so clamp it to what we can do. ␊
- Takes function pointer to function for reading the spd_nvram. Usefull␊
for faking data or hardcode a module without the nvram.␊
- fix other user for above change␊
- fix some comments.␊
␊
* Patches by Brian Waite, 26 Feb 2003:␊
- fix port for evb64260 board␊
- fix PCI for evb64260 board␊
- fix PCI scan␊
␊
* Patch by Reinhard Meyer, 1 Mar 2003:␊
Add support for EMK TOP860 Module␊
␊
* Patch by Yuli Barcohen, 02 Mar 2003:␊
Add SPD EEPROM support for MPC8260ADS board␊
␊
* Patch by Robert Schwebel, 21 Jan 2003:␊
- Add support for Innokom board␊
- Don't complain if "install" fails␊
CREDITS
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E: dan@netx4.com␊
D: FADSROM, the grandfather of all of this␊
␊
N: Reinhard Meyer␊
E: r.meyer@emk-elektronik.de␊
D: Port to EMK TOP860 Module␊
␊
N: Jay Monkman␊
E: jtm@smoothsmoothie.com␊
D: EST SBC8260 support␊
E: jim@musenki.com␊
D: Support for MUSENKI board␊
␊
N: Rune Torgersen␊
E: <runet@innovsys.com>␊
D: Support for Motorola MPC8266ADS board␊
␊
N: David Updegraff␊
E: dave@cray.com␊
D: Port to Cray L1 board; DHCP vendor extensions␊
MAINTAINERS
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␊
␊
#########################################################################␊
# PowerPC Systems:␉␉␉␉␉␉␉#␊
#␉␉␉␉␉␉␉␉␉#␊
# Maintainer Name, Email Address␉␉␉␉␉#␊
#␉Board␉␉␉CPU␉␉␉␉␉#␊
␊
␉EVB64260_750CX␉␉MPC750CX␊
␊
Reinhard Meyer <r.meyer@emk-elektronik.de>␊
␊
␉TOP860␉␉␉MPC860␊
␊
Scott McNutt <smcnutt@artesyncp.com>␊
␊
␉EBONY␉␉␉PPC440GP␊
␉MUSENKI␉␉␉MPC8245/8241␊
␉Sandpoint8245␉␉MPC8245␊
␊
Rune Torgersen <runet@innovsys.com>␊
␊
␉MPC8266ADS␉␉MPC8266␊
␊
-------------------------------------------------------------------------␊
␊
Unknown / orphaned boards:␊
MAKEALL
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␉MBX␉␉MBX860T␉␉MHPC␉␉MVS1␉␉\␊
␉NETVIA␉␉NX823␉␉pcu_e␉␉R360MPI␉␉\␊
␉RPXClassic␉RPXlite␉␉RRvision␉SM850␉␉\␊
␉SPD823TS␉SXNI855T␉TQM823L␉␉TQM823L_LCD␉\␊
␉TQM850L␉␉TQM855L␉␉TQM860L␉␉TQM860L_FEC␉\␊
␉TTTech␉␉v37␉␉␉␉␉␉\␊
␉SPD823TS␉SXNI855T␉TOP860␉␉TQM823L␉␉\␊
␉TQM823L_LCD␉TQM850L␉␉TQM855L␉␉TQM860L␉␉\␊
␉TQM860L_FEC␉TTTech␉␉v37␉␉␉␉\␊
"␊
␊
#########################################################################␊
␊
LIST_8260="␉\␊
␉cogent_mpc8260␉CPU86␉␉ep8260␉␉gw8260␉␉\␊
␉hymod␉␉IPHASE4539␉MPC8260ADS␉PM826␉␉\␊
␉ppmc8260␉RPXsuper␉rsdproto␉sacsng␉␉\␊
␉sbc8260␉␉SCM␉␉TQM8260␉␉␉␉\␊
␉hymod␉␉IPHASE4539␉MPC8260ADS␉MPC8266ADS␉\␊
␉PM826␉␉ppmc8260␉RPXsuper␉rsdproto␉\␊
␉sacsng␉␉sbc8260␉␉SCM␉␉TQM8260␉␉\␊
"␊
␊
#########################################################################␊
Makefile
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SXNI855T_config:␉unconfig␊
␉@./mkconfig $(@:_config=) ppc mpc8xx sixnet␊
␊
# EMK MPC8xx based modules␊
TOP860_config:␉␉unconfig␊
␉@./mkconfig $(@:_config=) ppc mpc8xx top860 emk␊
␊
# Play some tricks for configuration selection␊
# All boards can come with 50 MHz (default), 66MHz or 80MHz clock,␊
# but only 855 and 860 boards may come with FEC␊
MPC8260ADS_config:␉unconfig␊
␉@./mkconfig $(@:_config=) ppc mpc8260 mpc8260ads␊
␊
MPC8266ADS_config:␉unconfig␊
␉@./mkconfig $(@:_config=) ppc mpc8260 mpc8266ads␊
␊
PM826_config␉\␊
PM826_ROMBOOT_config: unconfig␊
␉@./mkconfig $(call xtract_82xx,$@) ppc mpc8260 pm826␊
board/ebony/ebony.c
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*/␊
␊
␊
extern long int spd_sdram (void);␊
␊
#include <common.h>␊
#include "ebony.h"␊
#include <asm/processor.h>␊
#include <spd_sdram.h>␊
␊
#define BOOT_SMALL_FLASH␉32␉/* 00100000 */␊
#define FLASH_ONBD_N␉␉2␉/* 00000010 */␊
long int initdram (int board_type)␊
{␊
␉long dram_size = 0;␊
␉extern long spd_sdram (void);␊
␊
#if defined(CONFIG_SPD_EEPROM)␊
␉dram_size = spd_sdram ();␊
␉dram_size = spd_sdram (0);␊
#else␊
␉dram_size = fixed_sdram ();␊
#endif␊
board/emk/top860/Makefile
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#␊
# (C) Copyright 2000␊
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
#␊
# See file CREDITS for list of people who contributed to this␊
# project.␊
#␊
# This program is free software; you can redistribute it and/or␊
# modify it under the terms of the GNU General Public License as␊
# published by the Free Software Foundation; either version 2 of␊
# the License, or (at your option) any later version.␊
#␊
# This program is distributed in the hope that it will be useful,␊
# but WITHOUT ANY WARRANTY; without even the implied warranty of␊
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
# GNU General Public License for more details.␊
#␊
# You should have received a copy of the GNU General Public License␊
# along with this program; if not, write to the Free Software␊
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
# MA 02111-1307 USA␊
#␊
␊
include $(TOPDIR)/config.mk␊
␊
LIB␉= lib$(BOARD).a␊
␊
OBJS␉= $(BOARD).o flash.o␊
␊
$(LIB):␉.depend $(OBJS)␊
␉$(AR) crv $@ $^␊
␊
#########################################################################␊
␊
.depend:␉Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)␊
␉␉$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@␊
␊
sinclude .depend␊
␊
#########################################################################␊
board/emk/top860/flash.c
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/*␊
* (C) Copyright 2003␊
* EMK Elektronik GmbH <www.emk-elektronik.de>␊
* Reinhard Meyer <r.meyer@emk-elektronik.de>␊
*␍␊
* copied from the BMW Port - seems that its similiar enough␍␊
* to be easily adaped ;) --- Well, it turned out to become a␍␊
* merger between parts of the EMKstax Flash routines and the␍␊
* BMW funtion frames...␍␊
*␊
* (C) Copyright 2000␊
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
#include <common.h>␊
#include <mpc8xx.h>␊
␊
#define␉FLASH_WORD_SIZE␉␉unsigned short␊
#define FLASH_WORD_WIDTH␉(sizeof (FLASH_WORD_SIZE))␍␊
␍␊
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */␊
␍␊
/*-----------------------------------------------------------------------␊
* Functions␊
*/␊
static int write_word (flash_info_t *info, ulong dest, ulong data);␊
␊
␊
/*****************************************************************************␍␊
* software product ID entry/exit␍␊
*****************************************************************************/␍␊
static void FlashProductIdMode (␍␊
␉volatile FLASH_WORD_SIZE *b,␍␊
␉int on_off)␍␊
{␍␊
␉b[0x5555] = 0xaa;␍␊
␉b[0x2aaa] = 0x55;␍␊
␉b[0x5555] = on_off ? 0x90 : 0xf0;␍␊
}␍␊
␍␊
/*****************************************************************************␍␊
* sector erase start␍␊
*****************************************************************************/␍␊
static void FlashSectorErase (␍␊
␉volatile FLASH_WORD_SIZE *b,␍␊
␉volatile FLASH_WORD_SIZE *a)␍␊
{␍␊
␉b[0x5555] = 0xaa;␍␊
␉b[0x2aaa] = 0x55;␍␊
␉b[0x5555] = 0x80;␍␊
␉b[0x5555] = 0xaa;␍␊
␉b[0x2aaa] = 0x55;␍␊
␉a[0] = 0x30;␍␊
}␍␊
␍␊
/*****************************************************************************␍␊
* program a word␍␊
*****************************************************************************/␍␊
static void FlashProgWord (␍␊
␉volatile FLASH_WORD_SIZE *b,␍␊
␉volatile FLASH_WORD_SIZE *a,␍␊
␉FLASH_WORD_SIZE v)␍␊
{␍␊
␉b[0x5555] = 0xaa;␍␊
␉b[0x2aaa] = 0x55;␍␊
␉b[0x5555] = 0xa0;␍␊
␉a[0] = v;␍␊
}␍␊
␍␊
/*****************************************************************************␍␊
* reset bank, back to read mode␍␊
*****************************************************************************/␍␊
static void FlashReset (volatile FLASH_WORD_SIZE *b)␍␊
{␍␊
␉b[0] = 0xf0;␍␊
}␍␊
␍␊
/*****************************************************************************␍␊
* identify FLASH chip␍␊
* this code is a stripped version of the FlashGetType() function in EMKstax␍␊
*****************************************************************************/␍␊
unsigned long flash_init (void)␊
{␍␊
␉volatile FLASH_WORD_SIZE * const flash = (volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE;␍␊
␉FLASH_WORD_SIZE␉manu, dev;␍␊
␉flash_info_t * const pflinfo = &flash_info[0];␍␊
␉int j;␍␊
␍␊
␉/* get Id Bytes */␍␊
␉FlashProductIdMode (flash, 1);␍␊
␉manu = flash[0];␍␊
␉dev = flash[1];␍␊
␉FlashProductIdMode (flash, 0);␍␊
␍␊
␉pflinfo->size = 0;␍␊
␉pflinfo->sector_count = 0;␍␊
␉pflinfo->flash_id = 0xffffffff;␍␊
␉pflinfo->portwidth = FLASH_CFI_16BIT;␍␊
␉pflinfo->chipwidth = FLASH_CFI_BY16;␍␊
␍␊
␉switch (manu&0xff)␍␊
␉{␍␊
␉case 0x01:␉/* AMD */␍␊
␉␉pflinfo->flash_id = FLASH_MAN_AMD;␍␊
␉␉switch (dev&0xff)␍␊
␉␉{␍␊
␉␉case 0x49:␍␊
␉␉␉pflinfo->size = 0x00200000;␍␊
␉␉␉pflinfo->sector_count = 35;␍␊
␉␉␉pflinfo->flash_id |= FLASH_AM160B;␍␊
␉␉␉pflinfo->start[0] = CFG_FLASH_BASE;␍␊
␉␉␉pflinfo->start[1] = CFG_FLASH_BASE + 0x4000;␍␊
␉␉␉pflinfo->start[2] = CFG_FLASH_BASE + 0x6000;␍␊
␉␉␉pflinfo->start[3] = CFG_FLASH_BASE + 0x8000;␍␊
␉␉␉for (j = 4; j < 35; j++)␍␊
␉␉␉{␍␊
␉␉␉␉pflinfo->start[j] = CFG_FLASH_BASE + 0x00010000 * (j-3);␍␊
␉␉␉}␍␊
␉␉␉break;␍␊
␍␊
␉␉case 0xf9:␍␊
␉␉␉pflinfo->size = 0x00400000;␍␊
␉␉␉pflinfo->sector_count = 71;␍␊
␉␉␉pflinfo->flash_id |= FLASH_AM320B;␍␊
␉␉␉pflinfo->start[0] = CFG_FLASH_BASE;␍␊
␉␉␉pflinfo->start[1] = CFG_FLASH_BASE + 0x4000;␍␊
␉␉␉pflinfo->start[2] = CFG_FLASH_BASE + 0x6000;␍␊
␉␉␉pflinfo->start[3] = CFG_FLASH_BASE + 0x8000;␍␊
␉␉␉for (j = 0; j < 8; j++)␍␊
␉␉␉{␍␊
␉␉␉␉pflinfo->start[j] = CFG_FLASH_BASE + 0x00002000 * (j);␍␊
␉␉␉}␍␊
␉␉␉for (j = 8; j < 71; j++)␍␊
␉␉␉{␍␊
␉␉␉␉pflinfo->start[j] = CFG_FLASH_BASE + 0x00010000 * (j-7);␍␊
␉␉␉}␍␊
␉␉␉break;␍␊
␍␊
␉␉default:␍␊
␉␉␉printf ("unknown AMD dev=%x ", dev);␍␊
␉␉␉pflinfo->flash_id |= FLASH_UNKNOWN;␍␊
␉␉}␍␊
␉␉break;␍␊
␍␊
␉default:␍␊
␉␉printf ("unknown manu=%x ", manu);␍␊
␉}␍␊
␉return pflinfo->size;␍␊
}␊
␊
/*****************************************************************************␍␊
* print info about a FLASH␍␊
*****************************************************************************/␍␊
void flash_print_info (flash_info_t *info)␊
{␍␊
␉static const char␉unk[] = "Unknown";␍␊
␉unsigned int␉␉i;␍␊
␉const char␉␉␉*mfct=unk,␍␊
␉␉␉␉␉␉*type=unk;␍␊
␍␊
␉if(info->flash_id != FLASH_UNKNOWN)␍␊
␉{␍␊
␉␉switch (info->flash_id & FLASH_VENDMASK)␍␊
␉␉{␍␊
␉␉case FLASH_MAN_AMD:␍␊
␉␉␉mfct = "AMD";␍␊
␉␉␉break;␍␊
␉␉}␍␊
␍␊
␉␉switch (info->flash_id & FLASH_TYPEMASK)␍␊
␉␉{␍␊
␉␉case FLASH_AM160B:␍␊
␉␉␉type = "AM29LV160B (16 Mbit, bottom boot sect)";␍␊
␉␉␉break;␍␊
␉␉case FLASH_AM320B:␍␊
␉␉␉type = "AM29LV320B (32 Mbit, bottom boot sect)";␍␊
␉␉␉break;␍␊
␉␉}␍␊
␉}␍␊
␍␊
␉printf (␍␊
␉␉"\n Brand: %s Type: %s\n"␍␊
␉␉" Size: %lu KB in %d Sectors\n",␍␊
␉␉mfct,␍␊
␉␉type,␍␊
␉␉info->size >> 10,␍␊
␉␉info->sector_count␍␊
␉␉);␍␊
␍␊
␉printf (" Sector Start Addresses:");␍␊
␍␊
␉for (i = 0; i < info->sector_count; i++)␍␊
␉{␍␊
␉␉unsigned long␉size;␍␊
␉␉unsigned int␉erased;␍␊
␉␉unsigned long␉*flash = (unsigned long *) info->start[i];␍␊
␍␊
␉␉/*␍␊
␉␉ * Check if whole sector is erased␍␊
␉␉ */␍␊
␉␉size =␍␊
␉␉␉(i != (info->sector_count - 1)) ?␍␊
␉␉␉(info->start[i + 1] - info->start[i]) >> 2 :␍␊
␉␉(info->start[0] + info->size - info->start[i]) >> 2;␍␊
␍␊
␉␉for (␍␊
␉␉␉flash = (unsigned long *) info->start[i], erased = 1;␍␊
␉␉␉␉(flash != (unsigned long *) info->start[i] + size) && erased;␍␊
␉␉␉␉␉flash++␍␊
␉␉␉)␍␊
␉␉␉erased = *flash == ~0x0UL;␍␊
␍␊
␉␉printf (␍␊
␉␉␉"%s %08lX %s %s",␍␊
␉␉␉(i % 5) ? "" : "\n ",␍␊
␉␉␉info->start[i],␍␊
␉␉␉erased ? "E" : " ",␍␊
␉␉␉info->protect[i] ? "RO" : " "␍␊
␉␉␉);␍␊
␉}␍␊
␍␊
␉puts ("\n");␍␊
␉return;␍␊
}␊
␊
/*****************************************************************************␍␊
* erase one or more sectors␍␊
*****************************************************************************/␍␊
int␉flash_erase (flash_info_t *info, int s_first, int s_last)␊
{␍␊
␉volatile FLASH_WORD_SIZE␉*addr = (FLASH_WORD_SIZE *)(info->start[0]);␍␊
␉int␉␉␉␉␉␉␉flag,␍␊
␉␉␉␉␉␉␉␉prot,␍␊
␉␉␉␉␉␉␉␉sect,␍␊
␉␉␉␉␉␉␉␉l_sect;␍␊
␉ulong␉␉␉␉␉␉start,␍␊
␉␉␉␉␉␉␉␉now,␍␊
␉␉␉␉␉␉␉␉last;␍␊
␍␊
␉if ((s_first < 0) || (s_first > s_last))␍␊
␉{␍␊
␉␉if (info->flash_id == FLASH_UNKNOWN)␍␊
␉␉{␍␊
␉␉␉printf ("- missing\n");␍␊
␉␉}␍␊
␉␉else␍␊
␉␉{␍␊
␉␉␉printf ("- no sectors to erase\n");␍␊
␉␉}␍␊
␉␉return 1;␍␊
␉}␍␊
␍␊
␉if ((info->flash_id == FLASH_UNKNOWN) ||␍␊
␉␉(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP)))␍␊
␉{␍␊
␉␉printf ("Can't erase unknown flash type - aborted\n");␍␊
␉␉return 1;␍␊
␉}␍␊
␍␊
␉prot = 0;␍␊
␉for (sect=s_first; sect<=s_last; ++sect)␍␊
␉{␍␊
␉␉if (info->protect[sect])␍␊
␉␉{␍␊
␉␉␉prot++;␍␊
␉␉}␍␊
␉}␍␊
␍␊
␉if (prot)␍␊
␉{␍␊
␉␉printf ("- Warning: %d protected sectors will not be erased!\n",␍␊
␉␉␉prot);␍␊
␉}␍␊
␉else␍␊
␉{␍␊
␉␉printf ("\n");␍␊
␉}␍␊
␍␊
␉l_sect = -1;␍␊
␍␊
␉/* Disable interrupts which might cause a timeout here */␍␊
␉flag = disable_interrupts();␍␊
␍␊
␉/* Start erase on unprotected sectors */␍␊
␉for (sect = s_first; sect<=s_last; sect++)␍␊
␉{␍␊
␉␉if (info->protect[sect] == 0)␍␊
␉␉{ /* not protected */␍␊
␉␉␉FlashSectorErase ((FLASH_WORD_SIZE *)info->start[0], (FLASH_WORD_SIZE *)info->start[sect]);␍␊
␉␉␉l_sect = sect;␍␊
␉␉}␍␊
␉}␍␊
␍␊
␉/* re-enable interrupts if necessary */␍␊
␉if (flag)␍␊
␉␉enable_interrupts();␍␊
␍␊
␉/* wait at least 80us - let's wait 1 ms */␍␊
␉udelay (1000);␍␊
␍␊
␉/*␍␊
␉* We wait for the last triggered sector␍␊
␉*/␍␊
␉if (l_sect < 0)␍␊
␉␉goto DONE;␍␊
␍␊
␉start = get_timer (0);␍␊
␉last = start;␍␊
␉addr = (FLASH_WORD_SIZE *)info->start[l_sect];␍␊
␉while ((addr[0] & 0x0080) != 0x0080)␍␊
␉{␍␊
␉␉if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT)␍␊
␉␉{␍␊
␉␉␉printf ("Timeout\n");␍␊
␉␉␉return 1;␍␊
␉␉}␍␊
␉␉/* show that we're waiting */␍␊
␉␉if ((now - last) > 1000)␍␊
␉␉{ /* every second */␍␊
␉␉␉serial_putc ('.');␍␊
␉␉␉last = now;␍␊
␉␉}␍␊
␉}␍␊
␍␊
␉DONE:␍␊
␉/* reset to read mode */␍␊
␉FlashReset ((FLASH_WORD_SIZE *)info->start[0]);␍␊
␍␊
␉printf (" done\n");␍␊
␉return 0;␍␊
}␊
␊
/*****************************************************************************␍␊
* Copy memory to flash, returns:␊
* 0 - OK␊
* 1 - write timeout␊
* 2 - Flash not erased␊
*****************************************************************************/␍␊
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)␊
{␍␊
␉ulong␉␉cp,␍␊
␉␉␉␉wp,␍␊
␉␉␉␉data;␍␊
␉int␉␉␉i,␍␊
␉␉␉␉l,␍␊
␉␉␉␉rc;␍␊
␍␊
␉wp = (addr & ~(FLASH_WORD_WIDTH-1)); /* get lower word aligned address */␍␊
␍␊
␉/*␍␊
␉ * handle unaligned start bytes, if there are...␍␊
␉ */␍␊
␉if ((l = addr - wp) != 0)␍␊
␉{␍␊
␉␉data = 0;␍␊
␉␉␍␊
␉␉/* get the current before the new data into our data word */␍␊
␉␉for (i=0, cp=wp; i<l; ++i, ++cp)␍␊
␉␉{␍␊
␉␉␉data = (data << 8) | (*(uchar *)cp);␍␊
␉␉}␍␊
␉␉␍␊
␉␉/* now merge the to be programmed values */␍␊
␉␉for (; i<4 && cnt>0; ++i, ++cp, --cnt)␍␊
␉␉{␍␊
␉␉␉data = (data << 8) | *src++;␍␊
␉␉}␍␊
␍␊
␉␉/* get the current after the new data into our data word */␍␊
␉␉for (; cnt==0 && i<FLASH_WORD_WIDTH; ++i, ++cp)␍␊
␉␉{␍␊
␉␉␉data = (data << 8) | (*(uchar *)cp);␍␊
␉␉}␍␊
␍␊
␉␉/* now write the combined word */␍␊
␉␉if ((rc = write_word (info, wp, data)) != 0)␍␊
␉␉{␍␊
␉␉␉return (rc);␍␊
␉␉}␍␊
␉␉wp += FLASH_WORD_WIDTH;␍␊
␉}␍␊
␍␊
␉/*␍␊
␉ * handle word aligned part␍␊
␉ */␍␊
␉while (cnt >= FLASH_WORD_WIDTH)␍␊
␉{␍␊
␉␉data = 0;␍␊
␉␉for (i=0; i<FLASH_WORD_WIDTH; ++i)␍␊
␉␉{␍␊
␉␉␉data = (data << 8) | *src++;␍␊
␉␉}␍␊
␉␉if ((rc = write_word (info, wp, data)) != 0)␍␊
␉␉{␍␊
␉␉␉return (rc);␍␊
␉␉}␍␊
␉␉wp += FLASH_WORD_WIDTH;␍␊
␉␉cnt -= FLASH_WORD_WIDTH;␍␊
␉}␍␊
␍␊
␉if (cnt == 0)␍␊
␉{␍␊
␉␉return (0);␍␊
␉}␍␊
␍␊
␉/*␍␊
␉ * handle unaligned tail bytes, if there are...␍␊
␉ */␍␊
␉data = 0;␍␊
␍␊
␉/* now merge the to be programmed values */␍␊
␉for (i=0, cp=wp; i<FLASH_WORD_WIDTH && cnt>0; ++i, ++cp)␍␊
␉{␍␊
␉␉data = (data << 8) | *src++;␍␊
␉␉--cnt;␍␊
␉}␍␊
␍␊
␉/* get the current after the new data into our data word */␍␊
␉for (; i<FLASH_WORD_WIDTH; ++i, ++cp)␍␊
␉{␍␊
␉␉data = (data << 8) | (*(uchar *)cp);␍␊
␉}␍␊
␍␊
␉/* now write the combined word */␍␊
␉return (write_word (info, wp, data));␍␊
}␊
␊
/*****************************************************************************␍␊
* Write a word to Flash, returns:␊
* 0 - OK␊
* 1 - write timeout␊
* 2 - Flash not erased␊
*****************************************************************************/␍␊
static int write_word (flash_info_t *info, ulong dest, ulong data)␊
{␍␊
␉volatile FLASH_WORD_SIZE␉*addr2 = (FLASH_WORD_SIZE *)info->start[0];␍␊
␉volatile FLASH_WORD_SIZE␉*dest2 = (FLASH_WORD_SIZE *)dest;␍␊
␉FLASH_WORD_SIZE␉␉␉␉data2 = data;␍␊
␉ulong␉␉␉␉␉␉start;␍␊
␉int␉␉␉␉␉␉␉flag;␍␊
␍␊
␉/* Check if Flash is (sufficiently) erased */␍␊
␉if ((*dest2 & data2) != data2)␍␊
␉{␍␊
␉␉return (2);␍␊
␉}␍␊
␉␍␊
␉/* Disable interrupts which might cause a timeout here */␍␊
␉flag = disable_interrupts ();␍␊
␍␊
␉FlashProgWord (addr2, dest2, data2);␍␊
␍␊
␉/* re-enable interrupts if necessary */␍␊
␉if (flag)␍␊
␉␉enable_interrupts ();␍␊
␍␊
␉/* data polling for D7 */␍␊
␉start = get_timer (0);␍␊
␉while ((*dest2 & 0x0080) != (data2 & 0x0080))␍␊
␉{␍␊
␉␉if (get_timer (start) > CFG_FLASH_WRITE_TOUT)␍␊
␉␉{␍␊
␉␉␉return (1);␍␊
␉␉}␍␊
␉}␍␊
␍␊
␉return (0);␍␊
}␊
␊
/*-----------------------------------------------------------------------␊
*/␊
␍␊
board/emk/top860/top860.c
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/*␊
* (C) Copyright 2003␊
* EMK Elektronik GmbH <www.emk-elektronik.de>␊
* Reinhard Meyer <r.meyer@emk-elektronik.de>␊
*␊
* Board specific routines for the TOP860␊
*␊
* - initialisation␊
* - interface to VPD data (mac address, clock speeds)␊
* - memory controller␊
* - serial io initialisation␊
* - ethernet io initialisation␊
*␊
* -----------------------------------------------------------------␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.␉ See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
#include <common.h>␊
#include <commproc.h>␊
#include <mpc8xx.h>␊
␊
/*****************************************************************************␍␊
* UPM table for 60ns EDO RAM at 25 MHz bus/external clock␍␊
*****************************************************************************/␍␊
static const uint edo_60ns_25MHz_tbl[] = {␊
␍␊
/* single read (offset 0x00 in upm ram) */␍␊
0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00,␍␊
0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05,␍␊
/* burst read (offset 0x08 in upm ram) */␍␊
0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40,␍␊
0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48,␍␊
0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05,␍␊
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,␍␊
/* single write (offset 0x18 in upm ram) */␍␊
0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07,␍␊
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,␍␊
/* burst write (offset 0x20 in upm ram) */␍␊
0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c,␍␊
0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c,␍␊
0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05,␍␊
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,␍␊
/* refresh (offset 0x30 in upm ram) */␍␊
0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04,␍␊
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,␍␊
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,␍␊
/* exception (offset 0x3C in upm ram) */␍␊
0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05,␍␊
};␊
␊
/*****************************************************************************␍␊
* Print Board Identity␍␊
*****************************************************************************/␍␊
int checkboard (void)␊
{␊
␉puts ("Board:"CONFIG_IDENT_STRING"\n");␊
␉return (0);␊
}␊
␊
/*****************************************************************************␍␊
* Initialize DRAM controller␍␊
*****************************************************************************/␍␊
long int initdram (int board_type)␊
{␊
␉volatile immap_t *immap = (immap_t *) CFG_IMMR;␊
␉volatile memctl8xx_t *memctl = &immap->im_memctl;␊
␊
␉/*␊
␉ * Only initialize memory controller when running from FLASH.␊
␉ * When running from RAM, don't touch it.␊
␉ */␊
␉if ((ulong) initdram & 0xff000000)␍␊
␉{␍␊
␉␉volatile uint␉*addr1, *addr2;␍␊
␉␉uint␉␉␉i, j;␍␊
␊
␉␉upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,␍␊
␉␉␉sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));␊
␉␉memctl->memc_mptpr = 0x0200;␊
␉␉memctl->memc_mamr = 0x0ca20330;␊
␉␉memctl->memc_or2 = -CFG_DRAM_MAX | OR_CSNT_SAM;␊
␉␉memctl->memc_br2 = CFG_DRAM_BASE | BR_MS_UPMA | BR_V;␊
␉␉/*␍␊
␉␉ * Do 8 read accesses to DRAM␍␊
␉␉ */␍␊
␉␉addr1 = (volatile uint*) 0;␍␊
␉␉addr2 = (volatile uint*) 0x00400000;␍␊
␉␉for (i=0, j=0; i<8; i++)␍␊
␉␉␉j = addr1[0];␍␊
␉␉␍␊
␉␉/*␍␊
␉␉ * Now check whether we got 4MB or 16MB populated␍␊
␉␉ */␍␊
␉␉addr1[0] = 0x12345678;␍␊
␉␉addr1[1] = 0x9abcdef0;␍␊
␉␉addr2[0] = 0xfeedc0de;␍␊
␉␉addr2[1] = 0x47110815;␍␊
␉␉if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815)␍␊
␉␉{␍␊
␉␉␉/* only 4MB populated */␍␊
␉␉␉memctl->memc_or2 = -(CFG_DRAM_MAX/4) | OR_CSNT_SAM;␍␊
␉␉}␍␊
␉}␍␊
␍␊
␉return -(memctl->memc_or2 & 0xffff0000);␊
}␊
␍␊
/*****************************************************************************␍␊
* otherinits after RAM is there and we are relocated to RAM␍␊
* note: though this is an int function, nobody cares for the result!␍␊
*****************************************************************************/␍␊
int misc_init_r (void)␊
{␍␊
␉/* read 'factory' part of EEPROM */␍␊
␉uchar␉␉␉␉buf[81];␍␊
␉uchar␉␉␉␉*p;␍␊
␉uint␉␉␉␉length;␍␊
␉uint␉␉␉␉addr;␍␊
␉uint␉␉␉␉len;␍␊
␍␊
␉/* get length first */␍␊
␉addr = CFG_FACT_OFFSET;␍␊
␉if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2))␍␊
␉{␍␊
bailout:␍␊
␉␉printf ("cannot read factory configuration\n");␍␊
␉␉printf ("be sure to set ethaddr␉yourself!\n");␍␊
␉␉return 0;␍␊
␉}␊
␉length = buf[0] + (buf[1]<<8);␍␊
␉addr += 2;␍␊
␍␊
␉/* sanity check */␍␊
␉if (length < 20 || length > CFG_FACT_SIZE-2)␍␊
␉␉goto bailout;␍␊
␍␊
␉/* read lines */␍␊
␉while (length > 0)␍␊
␉{␍␊
␉␉/* read one line */␍␊
␉␉len = length > 80 ? 80 : length;␍␊
␉␉if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len))␍␊
␉␉␉goto bailout;␍␊
␉␉/* mark end of buffer */␍␊
␉␉buf[len] = 0;␍␊
␉␉/* search end of line */␍␊
␉␉for (p=buf; *p && *p != 0x0a; p++) ;␍␊
␉␉if (!*p)␍␊
␉␉␉goto bailout;␍␊
␉␉*p++ = 0;␍␊
␉␉/* advance to next line start */␍␊
␉␉length -= p-buf;␍␊
␉␉addr += p-buf;␍␊
␉␉/*printf ("%s\n", buf);*/␍␊
␉␉/* search for our specific entry */␍␊
␉␉if (!strncmp ((char *)buf, "[RLA/lan/Ethernet] ", 19))␍␊
␉␉{␍␊
␉␉␉setenv ("ethaddr", buf+19);␊
␉␉} ␍␊
␉␉else if (!strncmp ((char *)buf, "[BOARD/SERIAL] ", 15))␍␊
␉␉{␍␊
␉␉␉setenv ("serial#", buf+15);␊
␉␉} ␍␊
␉␉else if (!strncmp ((char *)buf, "[BOARD/TYPE] ", 13))␍␊
␉␉{␍␊
␉␉␉setenv ("board_id", buf+13);␊
␉␉} ␍␊
␉}␍␊
␉return (0);␊
}␊
␊
board/emk/top860/u-boot.lds
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/*␊
* (C) Copyright 2000␊
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
OUTPUT_ARCH(powerpc)␊
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);␊
/* Do we need any of these for elf?␊
__DYNAMIC = 0; */␊
SECTIONS␊
{␊
/* Read-only sections, merged into text segment: */␊
. = + SIZEOF_HEADERS;␊
.interp : { *(.interp) }␊
.hash : { *(.hash)␉␉}␊
.dynsym : { *(.dynsym)␉␉}␊
.dynstr : { *(.dynstr)␉␉}␊
.rel.text : { *(.rel.text)␉␉}␊
.rela.text : { *(.rela.text) ␉}␊
.rel.data : { *(.rel.data)␉␉}␊
.rela.data : { *(.rela.data) ␉}␊
.rel.rodata : { *(.rel.rodata) ␉}␊
.rela.rodata : { *(.rela.rodata) ␉}␊
.rel.got : { *(.rel.got)␉␉}␊
.rela.got : { *(.rela.got)␉␉}␊
.rel.ctors : { *(.rel.ctors)␉}␊
.rela.ctors : { *(.rela.ctors)␉}␊
.rel.dtors : { *(.rel.dtors)␉}␊
.rela.dtors : { *(.rela.dtors)␉}␊
.rel.bss : { *(.rel.bss)␉␉}␊
.rela.bss : { *(.rela.bss)␉␉}␊
.rel.plt : { *(.rel.plt)␉␉}␊
.rela.plt : { *(.rela.plt)␉␉}␊
.init : { *(.init)␉}␊
.plt : { *(.plt) }␊
.text :␊
{␊
cpu/mpc8xx/start.o␉(.text)␊
␊
*(.text)␊
*(.fixup)␊
*(.got1)␊
}␊
_etext = .;␊
PROVIDE (etext = .);␊
.rodata :␊
{␊
*(.rodata)␊
*(.rodata1)␊
}␊
.fini : { *(.fini) } =0␊
.ctors : { *(.ctors) }␊
.dtors : { *(.dtors) }␊
␊
/* Read-write section, merged into data segment: */␊
. = (. + 0x00FF) & 0xFFFFFF00;␊
_erotext = .;␊
PROVIDE (erotext = .);␊
.reloc :␊
{␊
*(.got)␊
_GOT2_TABLE_ = .;␊
*(.got2)␊
_FIXUP_TABLE_ = .;␊
*(.fixup)␊
}␊
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;␊
__fixup_entries = (. - _FIXUP_TABLE_)>>2;␊
␊
.data :␊
{␊
*(.data)␊
*(.data1)␊
*(.sdata)␊
*(.sdata2)␊
*(.dynamic)␊
CONSTRUCTORS␊
}␊
_edata = .;␊
PROVIDE (edata = .);␊
␊
__start___ex_table = .;␊
__ex_table : { *(__ex_table) }␊
__stop___ex_table = .;␊
␊
. = ALIGN(256);␊
__init_begin = .;␊
.text.init : { *(.text.init) }␊
.data.init : { *(.data.init) }␊
. = ALIGN(256);␊
__init_end = .;␊
␊
__bss_start = .;␊
.bss :␊
{␊
*(.sbss) *(.scommon)␊
*(.dynbss)␊
*(.bss)␊
*(COMMON)␊
}␊
_end = . ;␊
PROVIDE (end = .);␊
}␊
␊
board/emk/top860/u-boot.lds.debug
1
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/*␊
* (C) Copyright 2000␊
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
OUTPUT_ARCH(powerpc)␊
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);␊
/* Do we need any of these for elf?␊
__DYNAMIC = 0; */␊
SECTIONS␊
{␊
/* Read-only sections, merged into text segment: */␊
. = + SIZEOF_HEADERS;␊
.interp : { *(.interp) }␊
.hash : { *(.hash)␉␉}␊
.dynsym : { *(.dynsym)␉␉}␊
.dynstr : { *(.dynstr)␉␉}␊
.rel.text : { *(.rel.text)␉␉}␊
.rela.text : { *(.rela.text) ␉}␊
.rel.data : { *(.rel.data)␉␉}␊
.rela.data : { *(.rela.data) ␉}␊
.rel.rodata : { *(.rel.rodata) ␉}␊
.rela.rodata : { *(.rela.rodata) ␉}␊
.rel.got : { *(.rel.got)␉␉}␊
.rela.got : { *(.rela.got)␉␉}␊
.rel.ctors : { *(.rel.ctors)␉}␊
.rela.ctors : { *(.rela.ctors)␉}␊
.rel.dtors : { *(.rel.dtors)␉}␊
.rela.dtors : { *(.rela.dtors)␉}␊
.rel.bss : { *(.rel.bss)␉␉}␊
.rela.bss : { *(.rela.bss)␉␉}␊
.rel.plt : { *(.rel.plt)␉␉}␊
.rela.plt : { *(.rela.plt)␉␉}␊
.init : { *(.init)␉}␊
.plt : { *(.plt) }␊
.text :␊
{␊
/* WARNING - the following is hand-optimized to fit within␉*/␊
/* the sector layout of our flash chips!␉XXX FIXME XXX␉*/␊
␊
cpu/mpc8xx/start.o␉(.text)␊
common/dlmalloc.o␉(.text)␊
lib_generic/vsprintf.o␉(.text)␊
lib_generic/crc32.o␉␉(.text)␊
lib_ppc/extable.o␉(.text)␊
␊
. = env_offset;␊
common/environment.o(.text)␊
␊
*(.text)␊
*(.fixup)␊
*(.got1)␊
}␊
_etext = .;␊
PROVIDE (etext = .);␊
.rodata :␊
{␊
*(.rodata)␊
*(.rodata1)␊
}␊
.fini : { *(.fini) } =0␊
.ctors : { *(.ctors) }␊
.dtors : { *(.dtors) }␊
␊
/* Read-write section, merged into data segment: */␊
. = (. + 0x0FFF) & 0xFFFFF000;␊
_erotext = .;␊
PROVIDE (erotext = .);␊
.reloc :␊
{␊
*(.got)␊
_GOT2_TABLE_ = .;␊
*(.got2)␊
_FIXUP_TABLE_ = .;␊
*(.fixup)␊
}␊
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;␊
__fixup_entries = (. - _FIXUP_TABLE_)>>2;␊
␊
.data :␊
{␊
*(.data)␊
*(.data1)␊
*(.sdata)␊
*(.sdata2)␊
*(.dynamic)␊
CONSTRUCTORS␊
}␊
_edata = .;␊
PROVIDE (edata = .);␊
␊
__start___ex_table = .;␊
__ex_table : { *(__ex_table) }␊
__stop___ex_table = .;␊
␊
. = ALIGN(4096);␊
__init_begin = .;␊
.text.init : { *(.text.init) }␊
.data.init : { *(.data.init) }␊
. = ALIGN(4096);␊
__init_end = .;␊
␊
__bss_start = .;␊
.bss :␊
{␊
*(.sbss) *(.scommon)␊
*(.dynbss)␊
*(.bss)␊
*(COMMON)␊
}␊
_end = . ;␊
PROVIDE (end = .);␊
}␊
␊
board/evb64260/evb64260.c
315315
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322324
}␊
␊
void␊
after_reloc(gd_t *gd, ulong dest_addr)␊
after_reloc(ulong dest_addr)␊
{␊
␉DECLARE_GLOBAL_DATA_PTR;␊
␊
␉/* check to see if we booted from the sram. If so, move things␊
␉ * back to the way they should be. (we're running from main␊
␉ * memory at this point now */␊
board/evb64260/pci.c
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5758
......
7475
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......
117118
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119120
120
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121122
122123
123124
......
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......
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......
647664
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static const unsigned int pci_p2p_configuration[] = {␊
PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION};␊
␊
static unsigned int local_buses[] = { 0, 0};␊
/********************************************************************␊
* pciWriteConfigReg - Write to a PCI configuration register␊
* - Make sure the GT is configured as a master before writing␊
{␊
volatile unsigned int DataForAddrReg;␊
unsigned int functionNum;␊
unsigned int busNum = 0;␊
unsigned int busNum = PCI_BUS(pciDevNum);␊
unsigned int addr;␊
␊
if(pciDevNum > 32) /* illegal device Number */␊
volatile unsigned int DataForAddrReg;␊
␉unsigned int data;␊
unsigned int functionNum;␊
unsigned int busNum = 0;␊
unsigned int busNum = PCI_BUS(pciDevNum);␊
␊
if(pciDevNum > 32) /* illegal device Number */␊
return 0xffffffff;␊
␉␉␉␉pci_dev_t dev,␊
␉␉␉␉int offset, u32* value)␊
{␊
*value = pciReadConfigReg((PCI_HOST) hose->cfg_addr, offset, PCI_DEV(dev));␊
return 0;␊
␉int bus = PCI_BUS(dev);␊
␉␊
␉if ((bus == local_buses[0]) || (bus == local_buses[1])){␊
␉␉*value = pciReadConfigReg((PCI_HOST) hose->cfg_addr, offset, ␊
␉␉␉␉␉ PCI_DEV(dev));␊
␉} else {␊
␉␉*value = pciOverBridgeReadConfigReg((PCI_HOST) hose->cfg_addr, ␊
␉␉␉␉␉␉ offset, PCI_DEV(dev), bus);␊
␉}␊
␉return 0;␊
}␊
␊
static int gt_write_config_dword(struct pci_controller *hose,␊
␉␉␉␉ pci_dev_t dev,␊
␉␉␉␉ int offset, u32 value)␊
{␊
pciWriteConfigReg((PCI_HOST)hose->cfg_addr, offset, PCI_DEV(dev), value);␊
return 0;␊
␉int bus = PCI_BUS(dev);␊
␊
␉if ((bus == local_buses[0]) || (bus == local_buses[1])){␊
␉␉pciWriteConfigReg((PCI_HOST)hose->cfg_addr, offset, ␊
␉␉␉␉ PCI_DEV(dev), value);␊
␉} else {␊
␉␉pciOverBridgeWriteConfigReg((PCI_HOST)hose->cfg_addr, offset, ␊
␉␉␉␉␉ PCI_DEV(dev), value, bus);␊
␉}␊
␉return 0;␊
}␊
␊
/*␊
␊
pci0_hose.first_busno = 0;␊
pci0_hose.last_busno = 0xff;␊
␊
local_buses[0] = pci0_hose.first_busno;␊
/* PCI memory space */␊
pci_set_region(pci0_hose.regions + 0,␊
␉␉ CFG_PCI0_0_MEM_SPACE,␊
␊
pci1_hose.first_busno = pci0_hose.last_busno + 1;␊
pci1_hose.last_busno = 0xff;␊
pci1_hose.current_busno = pci0_hose.current_busno;␊
local_buses[1] = pci1_hose.first_busno;␊
␊
/* PCI memory space */␊
pci_set_region(pci1_hose.regions + 0,␊
board/lubbock/config.mk
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#␊
# Linux-Kernel is expected to be at c000'8000, entry c000'8000␊
#␊
# we load ourself to c170'0000, the upper 1 MB of second bank␊
#␊
# download areas is c800'0000␊
#␊
␊
␊
#TEXT_BASE = 0xa1700000␊
TEXT_BASE = 0xa3000000␊
#TEXT_BASE = 0␊
board/lubbock/flash.c
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/*␊
* (C) Copyright 2002␊
* (C) Copyright 2001␊
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net␊
*␊
* (C) Copyright 2002␊
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>␊
* Marius Groeger <mgroeger@sysgo.de>␊
* (C) Copyright 2001␊
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*/␊
␊
#include <common.h>␊
#include <linux/byteorder/swab.h>␊
␊
#define FLASH_BANK_SIZE 0x2000000␊
#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */␊
␊
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];␊
flash_info_t␉flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips␉*/␊
␊
/* Board support for 1 or 2 flash devices */␊
#define FLASH_PORT_WIDTH32␊
#undef FLASH_PORT_WIDTH16␊
␊
#ifdef FLASH_PORT_WIDTH16␊
#define FLASH_PORT_WIDTH␉␉ushort␊
#define FLASH_PORT_WIDTHV␉␉vu_short␊
#define SWAP(x) __swab16(x)␊
#else␊
#define FLASH_PORT_WIDTH␉␉ulong␊
#define FLASH_PORT_WIDTHV␉␉vu_long␊
#define SWAP(x) __swab32(x)␊
#endif␊
␊
#define FPW␉ FLASH_PORT_WIDTH␊
#define FPWV FLASH_PORT_WIDTHV␊
␊
#define mb() __asm__ __volatile__ ("" : : : "memory")␊
␊
/*-----------------------------------------------------------------------␊
* Functions␊
*/␊
static ulong flash_get_size (FPW *addr, flash_info_t *info);␊
static int write_data (flash_info_t *info, ulong dest, FPW data);␊
static void flash_get_offsets (ulong base, flash_info_t *info);␊
void inline spin_wheel(void);␊
␊
ulong flash_init(void)␊
/*-----------------------------------------------------------------------␊
*/␊
␊
unsigned long flash_init (void)␊
{␊
int i, j;␊
int i;␊
ulong size = 0;␊
␊
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)␊
{␊
␉ulong flashbase = 0;␊
␉flash_info[i].flash_id =␊
␉ (INTEL_MANUFACT & FLASH_VENDMASK) |␊
␉ (INTEL_ID_28F128J3 & FLASH_TYPEMASK);␊
␉flash_info[i].size = FLASH_BANK_SIZE;␊
␉flash_info[i].sector_count = CFG_MAX_FLASH_SECT;␊
␉memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);␊
switch (i)␊
{␊
case 0:␊
␉ flashbase = PHYS_FLASH_1;␊
flash_get_size((FPW *)PHYS_FLASH_1, &flash_info[i]);␊
␉ flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);␊
break;␊
case 1:␊
␉ flashbase = PHYS_FLASH_2;␊
flash_get_size((FPW *)PHYS_FLASH_2, &flash_info[i]);␊
␉ flash_get_offsets(PHYS_FLASH_2, &flash_info[i]);␊
break;␊
default:␊
␉ panic("configured to many flash banks!\n");␊
break;␊
}␊
␉for (j = 0; j < flash_info[i].sector_count; j++)␊
␉{␊
␉ flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;␊
␉}␊
␉size += flash_info[i].size;␊
}␊
␊
␊
/*-----------------------------------------------------------------------␊
*/␊
static void flash_get_offsets (ulong base, flash_info_t *info)␊
{␊
␉int i;␊
␊
␉if (info->flash_id == FLASH_UNKNOWN) {␊
␉␉return;␊
␉}␊
␊
␉if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {␊
␉␉for (i = 0; i < info->sector_count; i++) {␊
␉␉␉info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);␊
␉␉␉info->protect[i] = 0;␊
␉␉}␊
␉}␊
}␊
␊
/*-----------------------------------------------------------------------␊
*/␊
void flash_print_info (flash_info_t *info)␊
{␊
int i, j;␊
␉int i;␊
␊
for (j=0; j<CFG_MAX_FLASH_BANKS; j++)␊
{␊
switch (info->flash_id & FLASH_VENDMASK)␊
{␊
case (INTEL_MANUFACT & FLASH_VENDMASK):␊
␉ printf("Intel: ");␊
␉ break;␊
default:␊
␉ printf("Unknown Vendor ");␊
␉ break;␊
␉if (info->flash_id == FLASH_UNKNOWN) {␊
␉␉printf ("missing or unknown FLASH type\n");␊
␉␉return;␊
}␊
␊
switch (info->flash_id & FLASH_TYPEMASK)␊
{␊
case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):␊
␉ printf("28F128J3 (128Mbit)\n");␊
␉ break;␊
default:␊
␉ printf("Unknown Chip Type\n");␊
␉ goto Done;␊
␉ break;␊
␉switch (info->flash_id & FLASH_VENDMASK) {␊
␉␉case FLASH_MAN_INTEL:␉printf ("INTEL ");␉␉break;␊
␉␉default:␉␉printf ("Unknown Vendor ");␉break;␊
␉}␊
␊
␉switch (info->flash_id & FLASH_TYPEMASK) {␊
case FLASH_28F128J3A:␊
␉␉␉␉printf ("28F128J3A\n"); break;␊
␉default:␉␉printf ("Unknown Chip Type\n"); break;␊
}␊
␊
printf(" Size: %ld MB in %d Sectors\n",␊
␉printf (" Size: %ld MB in %d Sectors\n",␊
␉ info->size >> 20, info->sector_count);␊
␊
printf(" Sector Start Addresses:");␊
for (i = 0; i < info->sector_count; i++)␊
{␊
␉printf (" Sector Start Addresses:");␊
␉for (i=0; i<info->sector_count; ++i) {␊
␉ if ((i % 5) == 0)␊
␉ {␊
␉ printf ("\n ");␊
␉ }␊
␉ printf (" %08lX%s", info->start[i],␊
␉␉ info->protect[i] ? " (RO)" : " ");␊
␉␉printf (" %08lX%s",␊
␉␉␉info->start[i],␊
␉␉␉info->protect[i] ? " (RO)" : " "␊
␉␉);␊
}␊
printf ("\n");␊
info++;␊
␉return;␊
}␊
␊
/*␊
* The following code cannot be run from FLASH!␊
*/␊
static ulong flash_get_size (FPW *addr, flash_info_t *info)␊
{␊
␉volatile FPW value;␊
␊
␉/* Write auto select command: read Manufacturer ID */␊
␉addr[0x5555] = (FPW)0x00AA00AA;␊
␉addr[0x2AAA] = (FPW)0x00550055;␊
␉addr[0x5555] = (FPW)0x00900090;␊
␊
mb();␊
␉value = addr[0];␊
␊
switch (value) {␊
␊
case (FPW)INTEL_MANUFACT:␊
info->flash_id = FLASH_MAN_INTEL;␊
break;␊
␊
␉default:␊
␉␉info->flash_id = FLASH_UNKNOWN;␊
␉␉info->sector_count = 0;␊
␉␉info->size = 0;␊
␉␉addr[0] = (FPW)0x00FF00FF; /* restore read mode */␊
␉␉return (0);␉␉␉/* no or unknown flash␉*/␊
␉}␊
␊
mb();␊
␉value = addr[1];␉␉␉/* device ID␉␉*/␊
␊
switch (value) {␊
␊
case (FPW)INTEL_ID_28F128J3A:␊
info->flash_id += FLASH_28F128J3A;␊
info->sector_count = 128;␊
info->size = 0x02000000;␊
break; /* => 16 MB */␊
␊
␉default:␊
␉␉info->flash_id = FLASH_UNKNOWN;␊
␉␉break;␊
␉}␊
␊
␉if (info->sector_count > CFG_MAX_FLASH_SECT) {␊
␉␉printf ("** ERROR: sector count %d > max (%d) **\n",␊
␉␉␉info->sector_count, CFG_MAX_FLASH_SECT);␊
␉␉info->sector_count = CFG_MAX_FLASH_SECT;␊
}␊
␊
Done:␊
␉addr[0] = (FPW)0x00FF00FF; /* restore read mode */␊
␊
␉return (info->size);␊
}␊
␊
␊
/*-----------------------------------------------------------------------␊
*/␊
␊
int␉flash_erase (flash_info_t *info, int s_first, int s_last)␊
{␊
int flag, prot, sect;␊
int rc = ERR_OK;␊
␊
if (info->flash_id == FLASH_UNKNOWN)␊
␉return ERR_UNKNOWN_FLASH_TYPE;␊
␉ulong type, start, now, last;␊
␉int rcode = 0;␊
␊
if ((s_first < 0) || (s_first > s_last)) {␊
␉return ERR_INVAL;␊
␉␉if (info->flash_id == FLASH_UNKNOWN) {␊
␉␉␉printf ("- missing\n");␊
␉␉} else {␊
␉␉␉printf ("- no sectors to erase\n");␊
␉␉}␊
␉␉return 1;␊
}␊
␊
if ((info->flash_id & FLASH_VENDMASK) !=␊
␉(INTEL_MANUFACT & FLASH_VENDMASK)) {␊
␉return ERR_UNKNOWN_FLASH_VENDOR;␊
␉type = (info->flash_id & FLASH_VENDMASK);␊
␉if ((type != FLASH_MAN_INTEL)) {␊
␉␉printf ("Can't erase unknown flash type %08lx - aborted\n",␊
␉␉␉info->flash_id);␊
␉␉return 1;␊
}␊
␊
prot = 0;␊
␉ prot++;␊
␉}␊
}␊
if (prot)␊
␉return ERR_PROTECTED;␊
␊
/*␊
* Disable interrupts which might cause a timeout␊
* here. Remember that our exception vectors are␊
* at address 0 in the flash, and we don't want a␊
* (ticker) exception to happen while the flash␊
* chip is in programming mode.␊
*/␊
␉if (prot) {␊
␉␉printf ("- Warning: %d protected sectors will not be erased!\n",␊
␉␉␉prot);␊
␉} else {␊
␉␉printf ("\n");␊
␉}␊
␊
␉start = get_timer (0);␊
␉last = start;␊
␊
/* Disable interrupts which might cause a timeout here */␊
flag = disable_interrupts();␊
␊
/* Start erase on unprotected sectors */␊
for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {␊
␉for (sect = s_first; sect<=s_last; sect++) {␊
␉␉if (info->protect[sect] == 0) {␉/* not protected */␊
␉␉␉FPWV *addr = (FPWV *)(info->start[sect]);␊
␉␉␉FPW status;␊
␊
␉printf("Erasing sector %2d ... ", sect);␊
␊
␉/* arm simple, non interrupt dependent timer */␊
␉reset_timer_masked();␊
␊
␉if (info->protect[sect] == 0) {␉/* not protected */␊
␉ vu_short *addr = (vu_short *)(info->start[sect]);␊
␉␉␉*addr = (FPW)0x00500050;␉/* clear status register */␊
␉␉␉*addr = (FPW)0x00200020;␉/* erase setup */␊
␉␉␉*addr = (FPW)0x00D000D0;␉/* erase confirm */␊
␊
␉ *addr = 0x20;␉/* erase setup */␊
␉ *addr = 0xD0;␉/* erase confirm */␊
␊
␉ while ((*addr & 0x80) != 0x80) {␊
␉␉␉while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {␊
␉␉if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {␊
␉␉ *addr = 0xB0; /* suspend erase */␊
␉␉ *addr = 0xFF;␉/* reset to read mode */␊
␉␉ rc = ERR_TIMOUT;␊
␉␉ goto outahere;␊
␉␉}␊
␉ }␊
␊
␉ /* clear status register command */␊
␉ *addr = 0x50;␊
␉ /* reset to read mode */␊
␉ *addr = 0xFF;␊
␉␉␉␉␉printf ("Timeout\n");␊
␉␉␉␉␉*addr = (FPW)0x00B000B0; /* suspend erase␉ */␊
␉␉␉␉␉*addr = (FPW)0x00FF00FF; /* reset to read mode */␊
␉␉␉␉␉rcode = 1;␊
␉␉␉␉␉break;␊
␉}␊
␉printf("ok.\n");␊
}␊
if (ctrlc())␊
printf("User Interrupt!\n");␊
␊
outahere:␊
␉␉␉*addr = 0x00500050; /* clear status register cmd. */␊
␉␉␉*addr = 0x00FF00FF; /* resest to read mode */␊
␊
/* allow flash to settle - wait 10 ms */␊
udelay_masked(10000);␊
␊
if (flag)␊
enable_interrupts();␊
␊
return rc;␊
}␊
␊
/*-----------------------------------------------------------------------␊
* Copy memory to flash␊
*/␊
␊
static int write_word (flash_info_t *info, ulong dest, ushort data)␊
{␊
vu_short *addr = (vu_short *)dest, val;␊
int rc = ERR_OK;␊
int flag;␊
␊
/* Check if Flash is (sufficiently) erased␊
*/␊
if ((*addr & data) != data)␊
return ERR_NOT_ERASED;␊
␊
/*␊
* Disable interrupts which might cause a timeout␊
* here. Remember that our exception vectors are␊
* at address 0 in the flash, and we don't want a␊
* (ticker) exception to happen while the flash␊
* chip is in programming mode.␊
*/␊
flag = disable_interrupts();␊
␊
/* clear status register command */␊
*addr = 0x50;␊
␊
/* program set-up command */␊
*addr = 0x40;␊
␊
/* latch address/data */␊
*addr = data;␊
␊
/* arm simple, non interrupt dependent timer */␊
reset_timer_masked();␊
␊
/* wait while polling the status register */␊
while(((val = *addr) & 0x80) != 0x80)␊
{␊
␉if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {␊
␉ rc = ERR_TIMOUT;␊
␉ /* suspend program command */␊
␉ *addr = 0xB0;␊
␉ goto outahere;␊
␉}␊
}␊
␊
if(val & 0x1A) {␉/* check for error */␊
printf("\nFlash write error %02x at address %08lx\n",␊
␉ (int)val, (unsigned long)dest);␊
if(val & (1<<3)) {␊
␉ printf("Voltage range error.\n");␊
␉ rc = ERR_PROG_ERROR;␊
␉ goto outahere;␊
␉␉␉printf (" done\n");␊
}␊
if(val & (1<<1)) {␊
␉ printf("Device protect error.\n");␊
␉ rc = ERR_PROTECTED;␊
␉ goto outahere;␊
}␊
if(val & (1<<4)) {␊
␉ printf("Programming error.\n");␊
␉ rc = ERR_PROG_ERROR;␊
␉ goto outahere;␊
}␊
rc = ERR_PROG_ERROR;␊
goto outahere;␊
}␊
␊
outahere:␊
/* read array command */␊
*addr = 0xFF;␊
␊
if (flag)␊
enable_interrupts();␊
␊
return rc;␊
␉return rcode;␊
}␊
␊
/*-----------------------------------------------------------------------␊
* Copy memory to flash.␊
* Copy memory to flash, returns:␊
* 0 - OK␊
* 1 - write timeout␊
* 2 - Flash not erased␊
* 4 - Flash not identified␊
*/␊
␊
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)␊
{␊
ulong cp, wp;␊
ushort data;␊
int l;␊
int i, rc;␊
␉FPW data;␊
␉int count, i, l, rc, port_width;␊
␊
wp = (addr & ~1);␉/* get lower word aligned address */␊
␉if (info->flash_id == FLASH_UNKNOWN) {␊
␉␉return 4;␊
␉}␊
/* get lower word aligned address */␊
#ifdef FLASH_PORT_WIDTH16␊
␉wp = (addr & ~1);␊
␉port_width = 2;␊
#else␊
␉wp = (addr & ~3);␊
␉port_width = 4;␊
#endif␊
␊
/*␊
* handle unaligned start bytes␊
if ((l = addr - wp) != 0) {␊
␉data = 0;␊
␉for (i=0, cp=wp; i<l; ++i, ++cp) {␊
␉ data = (data >> 8) | (*(uchar *)cp << 8);␊
␉␉␉data = (data << 8) | (*(uchar *)cp);␊
␉}␊
␉for (; i<2 && cnt>0; ++i) {␊
␉ data = (data >> 8) | (*src++ << 8);␊
␉␉for (; i<port_width && cnt>0; ++i) {␊
␉␉␉data = (data << 8) | *src++;␊
␉ --cnt;␊
␉ ++cp;␊
␉}␊
␉for (; cnt==0 && i<2; ++i, ++cp) {␊
␉ data = (data >> 8) | (*(uchar *)cp << 8);␊
␉␉for (; cnt==0 && i<port_width; ++i, ++cp) {␊
␉␉␉data = (data << 8) | (*(uchar *)cp);␊
␉}␊
␊
␉if ((rc = write_word(info, wp, data)) != 0) {␊
␉␉if ((rc = write_data(info, wp, SWAP(data))) != 0) {␊
␉ return (rc);␊
␉}␊
␉wp += 2;␊
␉␉wp += port_width;␊
}␊
␊
/*␊
* handle word aligned part␊
*/␊
while (cnt >= 2) {␊
␉data = *((vu_short*)src);␊
␉if ((rc = write_word(info, wp, data)) != 0) {␊
␉count = 0;␊
␉while (cnt >= port_width) {␊
␉␉data = 0;␊
␉␉for (i=0; i<port_width; ++i) {␊
␉␉␉data = (data << 8) | *src++;␊
␉␉}␊
␉␉if ((rc = write_data(info, wp, SWAP(data))) != 0) {␊
␉ return (rc);␊
␉}␊
␉src += 2;␊
␉wp += 2;␊
␉cnt -= 2;␊
␉␉wp += port_width;␊
␉␉cnt -= port_width;␊
␉␉if (count++ > 0x800)␊
␉␉{␊
spin_wheel();␊
␉␉␉count = 0;␊
␉␉}␊
}␊
␊
if (cnt == 0) {␊
␉return ERR_OK;␊
␉␉return (0);␊
}␊
␊
/*␊
* handle unaligned tail bytes␊
*/␊
data = 0;␊
for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {␊
␉data = (data >> 8) | (*src++ << 8);␊
␉for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {␊
␉␉data = (data << 8) | *src++;␊
␉--cnt;␊
}␊
for (; i<2; ++i, ++cp) {␊
␉data = (data >> 8) | (*(uchar *)cp << 8);␊
␉for (; i<port_width; ++i, ++cp) {␊
␉␉data = (data << 8) | (*(uchar *)cp);␊
␉}␊
␊
␉return (write_data(info, wp, SWAP(data)));␊
}␊
␊
/*-----------------------------------------------------------------------␊
* Write a word or halfword to Flash, returns:␊
* 0 - OK␊
* 1 - write timeout␊
* 2 - Flash not erased␊
*/␊
static int write_data (flash_info_t *info, ulong dest, FPW data)␊
{␊
␉FPWV *addr = (FPWV *)dest;␊
␉ulong status;␊
␉ulong start;␊
␉int flag;␊
␊
␉/* Check if Flash is (sufficiently) erased */␊
␉if ((*addr & data) != data) {␊
␉␉printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);␊
␉␉return (2);␊
␉}␊
␉/* Disable interrupts which might cause a timeout here */␊
␉flag = disable_interrupts();␊
␊
␉*addr = (FPW)0x00400040;␉␉/* write setup */␊
␉*addr = data;␊
␊
␉/* arm simple, non interrupt dependent timer */␊
␉reset_timer_masked();␊
␊
␉/* wait while polling the status register */␊
␉while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {␊
␉␉if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {␊
␉␉␉*addr = (FPW)0x00FF00FF;␉/* restore read mode */␊
␉␉␉return (1);␊
␉␉}␊
}␊
␊
return write_word(info, wp, data);␊
␉*addr = (FPW)0x00FF00FF;␉/* restore read mode */␊
␊
␉return (0);␊
}␊
␊
void inline␊
spin_wheel(void)␊
{␊
static int r=0,p=0;␊
static char w[] = "\\/-";␊
␊
printf("\010%c", w[p]);␊
(++p == 3) ? (p = 0) : 0;␊
}␊
␊
board/lubbock/lubbock.c
4747
4848
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50
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5151
5252
5353
......
6262
6363
6464
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6767
␉/* adress of boot parameters */␊
␉gd->bd->bi_boot_params = 0xa0000100;␊
␊
␉return 1;␊
␉return 0;␊
}␊
␊
int dram_init (void)␊
␉gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;␊
␉gd->bd->bi_dram[3].start = PHYS_SDRAM_4;␊
␉gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;␊
␉return PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + PHYS_SDRAM_3_SIZE +␊
␉␉␉PHYS_SDRAM_4_SIZE;␊
␊
return 0;␊
}␊
board/lubbock/memsetup.S
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.endm␊
␊
␊
/*␊
* ␉Memory setup␊
*/␊
␊
.globl memsetup␊
memsetup:␊
␊
mov r10, lr␊
␊
/* Set up GPIO pins first */␊
␉/* Set up GPIO pins first ----------------------------------------- */␊
␊
␉ldr␉␉r0,␉=GPSR0␊
␉ldr␉␉r1,␉=CFG_GPSR0_VAL␊
␉ldr␉␉r1,␉=CFG_GAFR2_U_VAL␊
␉str␉␉r1, [r0]␊
␊
/* enable GPIO pins */␊
␉ldr␉␉r0,␉=PSSR␊
␉ldr␉r0,␉=PSSR␉␉/* enable GPIO pins */␊
␉ldr␉␉r1,␉=CFG_PSSR_VAL␊
␉str␉␉r1, [r0]␊
␊
ldr r3, =MSC1␉␉ ␉␉/* low - bank 2 Lubbock Registers / SRAM */␊
ldr r2, =CFG_MSC1_VAL␉␉␉/* high - bank 3 Ethernet Controller */␊
str r2, [r3] ␉␉␉␉/* need to set MSC1 before trying to write to the HEX LEDs */␊
ldr r2, [r3] ␉␉␉␉/* need to read it back to make sure the value latches (see MSC section of manual) */␊
␊
ldr r1, =LED_BLANK␊
mov r0, #0xFF␊
str r0, [r1] ␉␉/* turn on hex leds */␊
␊
loop:␊
ldr␉␉r0, =0xB0070001␊
ldr ␉r1, =_LED␊
str ␉r0, [r1] ␉␉␉␉␉␉␉/* hex display */␊
␊
/*********************************************************************␊
Initlialize Memory Controller␊
␉ The sequence below is based on the recommended init steps detailed␊
␉ in the EAS, chapter 5 (Chapter 10, Operating Systems Developers Guide)␊
␊
␊
pause for 200 uSecs- allow internal clocks to settle␊
␉ *Note: only need this if hard reset... doing it anyway for now␊
*/␊
␊
␉@ ---- Wait 200 usec␊
␉ldr r3, =OSCR @ reset the OS Timer Count to zero␊
␉/* ---------------------------------------------------------------- */␊
␉/* Enable memory interface */␊
␉/* */␊
␉/* The sequence below is based on the recommended init steps */␊
␉/* detailed in the Intel PXA250 Operating Systems Developers Guide, */␊
␉/* Chapter 10. */␊
␉/* ---------------------------------------------------------------- */␊
␊
␉/* ---------------------------------------------------------------- */␊
␉/* Step 1: Wait for at least 200 microsedonds to allow internal */␊
␉/* clocks to settle. Only necessary after hard reset... */␊
␉/* FIXME: can be optimized later */␊
␉/* ---------------------------------------------------------------- */␊
␊
␉ldr r3, =OSCR␉␉␉/* reset the OS Timer Count to zero */␊
␉mov r2, #0␊
␉str r2, [r3]␊
␉ldr r4, =0x300␉␉␉@ really 0x2E1 is about 200usec, so 0x300 should be plenty␊
␉ldr r4, =0x300␉␉␉/* really 0x2E1 is about 200usec, */␊
␉␉␉␉␉/* so 0x300 should be plenty */␊
1:␊
␉ldr r2, [r3]␊
␉cmp r4, r2␊
␉bgt 1b␊
␊
mem_init:␊
@ get memory controller base address␊
ldr r1, =MEMC_BASE␊
␊
@****************************************************************************␊
@ Step 1␊
@␊
ldr r1, =MEMC_BASE␉␉/* get memory controller base addr. */␊
␊
@ write msc0, read back to ensure data latches␊
@␊
␉/* ---------------------------------------------------------------- */␊
␉/* Step 2a: Initialize Asynchronous static memory controller */␊
␉/* ---------------------------------------------------------------- */␊
␊
␉/* MSC registers: timing, bus width, mem type */␊
␊
/* MSC0: nCS(0,1) */␊
ldr r2, =CFG_MSC0_VAL␊
str r2, [r1, #MSC0_OFFSET]␊
ldr r2, [r1, #MSC0_OFFSET]␊
␊
@ write msc1␊
ldr r2, [r1, #MSC0_OFFSET]␉/* read back to ensure */␊
␉␉␉␉␉␉/* that data latches */␊
/* MSC1: nCS(2,3) */␊
ldr r2, =CFG_MSC1_VAL␊
str r2, [r1, #MSC1_OFFSET]␊
ldr r2, [r1, #MSC1_OFFSET]␊
␊
@ write msc2␊
␉/* MSC2: nCS(4,5) */␊
ldr r2, =CFG_MSC2_VAL␊
str r2, [r1, #MSC2_OFFSET]␊
ldr r2, [r1, #MSC2_OFFSET]␊
␊
@ write mecr␊
␉/* ---------------------------------------------------------------- */␊
␉/* Step 2b: Initialize Card Interface */␊
␉/* ---------------------------------------------------------------- */␊
␊
␉/* MECR: Memory Expansion Card Register */␊
ldr r2, =CFG_MECR_VAL␊
str r2, [r1, #MECR_OFFSET]␊
␉ldr␉r2,␉[r1, #MECR_OFFSET]␊
␊
@ write mcmem0␊
␉/* MCMEM0: Card Interface slot 0 timing */␊
ldr r2, =CFG_MCMEM0_VAL␊
str r2, [r1, #MCMEM0_OFFSET]␊
␉ldr␉r2,␉[r1, #MCMEM0_OFFSET]␊
␊
@ write mcmem1␊
/* MCMEM1: Card Interface slot 1 timing */␊
ldr r2, =CFG_MCMEM1_VAL␊
str r2, [r1, #MCMEM1_OFFSET]␊
␉ldr␉r2,␉[r1, #MCMEM1_OFFSET]␊
␊
@ write mcatt0␊
␉/* MCATT0: Card Interface Attribute Space Timing, slot 0 */␊
ldr r2, =CFG_MCATT0_VAL␊
str r2, [r1, #MCATT0_OFFSET]␊
␉ldr␉r2,␉[r1, #MCATT0_OFFSET]␊
␊
@ write mcatt1␊
␉/* MCATT1: Card Interface Attribute Space Timing, slot 1 */␊
ldr r2, =CFG_MCATT1_VAL␊
str r2, [r1, #MCATT1_OFFSET]␊
␉ldr␉r2,␉[r1, #MCATT1_OFFSET]␊
␊
@ write mcio0␊
␉/* MCIO0: Card Interface I/O Space Timing, slot 0 */␊
ldr r2, =CFG_MCIO0_VAL␊
str r2, [r1, #MCIO0_OFFSET]␊
␉ldr␉r2,␉[r1, #MCIO0_OFFSET]␊
␊
@ write mcio1␊
␉/* MCIO1: Card Interface I/O Space Timing, slot 1 */␊
ldr r2, =CFG_MCIO1_VAL␊
str r2, [r1, #MCIO1_OFFSET]␊
␉ldr␉r2,␉[r1, #MCIO1_OFFSET]␊
␊
@-------------------------------------------------------␊
@ 3rd bullet, Step 1␊
@␊
␉/* ---------------------------------------------------------------- */␊
/* Step 2c: Write FLYCNFG FIXME: what's that??? */␊
/* ---------------------------------------------------------------- */␊
␊
@ get the mdrefr settings␊
ldr r3, =CFG_MDREFR_VAL_100␊
␊
@ extract DRI field (we need a valid DRI field)␊
@␊
ldr r2, =0xFFF␊
␉/* ---------------------------------------------------------------- */␊
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */␊
/* ---------------------------------------------------------------- */␊
␊
@ valid DRI field in r3␊
@␊
and r3, r3, r2␊
␉/* Before accessing MDREFR we need a valid DRI field, so we set */␊
␉/* this to power on defaults + DRI field. */␊
␊
@ get the reset state of MDREFR␊
@␊
ldr r3, =CFG_MDREFR_VAL␊
ldr r2, =0xFFF␊
and r3, r3, r2␊
␉ldr␉r4,␉=0x03ca4000␊
orr r4, r4, r3␊
␉str␉r4,␉[r1, #MDREFR_OFFSET]␉/* write back MDREFR */␊
ldr r4, [r1, #MDREFR_OFFSET]␊
␊
@ clear the DRI field␊
@␊
bic r4, r4, r2␊
␊
@ insert the valid DRI field loaded above␊
@␊
orr r4, r4, r3␊
␊
@ write back mdrefr␊
@␊
str r4, [r1, #MDREFR_OFFSET]␊
␊
@ *Note: preserve the mdrefr value in r4 *␊
␊
@****************************************************************************␊
@ Step 2␊
@␊
/* This should be for SRAM, why is it commented out??? */␊
␊
@ fetch sxcnfg value␊
@␊
@ldr r2, =0␊
@ write back sxcnfg␊
@str r2, [r1, #SXCNFG_OFFSET]␊
␊
/* @if sxcnfg=0, don't program for synch-static memory */␊
@cmp r2, #0␊
@beq 1f␊
␊
@program sxmrs␊
@ldr r2, =SXMRS_SETTINGS␊
@str r2, [r1, #SXMRS_OFFSET]␊
␊
␊
@****************************************************************************␊
@ Step 3␊
@␊
␊
@ Assumes previous mdrefr value in r4, if not then read current mdrefr␊
␊
@ clear the free-running clock bits␊
@ (clear K0Free, K1Free, K2Free␊
@␊
bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)␊
␊
@ set K1RUN if bank 0 installed␊
@␊
orr r4, r4, #0x00010000␊
␊
␊
␊
#ifdef THIS␊
@<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<␊
@<!<!<!<!<!<!<!<!<!<!<! Begin INSERT 1 <!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<␊
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@␊
@ Lubbock: Allow the user to select the {T/R/M} with predetermined␊
@ SDCLK. Based on Table 3-1 in PXA250 and PXA210 Dev Man.␊
@␊
@ * = Must set MDREFR.K1DB2 to halve the MemClk for desired SDCLK[1]␊
@␊
@ S25, S26 used to provide all 400 MHz BIN values for Cotulla (0,0 - 1,3)␊
@ S25, S26 used to provide all 200 MHz BIN values for Sabinal␊
@␊
@ S23: Force the halving of MemClk when deriving SDCLK[1]␊
@ DOT: no override !DOT: halve (if not already forced half)␊
/* @ *For certain MemClks, SDCLK's derivation is forced to be halved */␊
@␊
@ S24: Run/Turbo.␊
@ DOT: Run mode !DOT: Turbo mode␊
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@␊
␊
@␊
@ Allow the user to control K1DB2 where applicable␊
@␊
@ Get the value of S23: @ 1 = DOT (unity), 0 = !DOT (halve it)␊
@␊
@ DOT: set K1DB2 (SDCLD = MemClk)␊
@ !DOT: clear K1DB2 (SDCLK = MemClk/2)␊
@␊
@ldr r2, =FPGA_REGS_BASE_PHYSICAL␊
␊
bl GET_S23 @ r3, r2 @ get the value of S23 in R0, i put the base adx of fpga in r3␊
␊
cmp r3, #0x0 @ is !DOT?␊
orreq r4, r4, #0x00020000 @ SDClk[1] = MemClk/2␊
bicne r4, r4, #0x00020000 @ SDClk[1] = MemClk␊
␊
@␊
@ Next, we need to look for S25,S26 selections that necessitate the␊
@ halving of MemClk to derive SDCLK[1]: (S25,S26)={03-0C, 10-13}␊
@ Override above S23-based selection accordingly.␊
@␊
ldr r2, =FPGA_REGS_BASE_PHYSICAL␊
bl GET_S25 @ r0, r2␊
@ get the value of S25 in R0, i put the base adx of fpga in r2␊
␊
␊
␊
ldr r2, =FPGA_REGS_BASE_PHYSICAL␊
BL GET_S26 @ r3, r2␊
@ get the value of S26 in R1, i put the base adx of fpga in r2␊
␊
orr r0, r0, r3 @ concatenate S25 & S26 vals␊
and r0, r0, #0xFF␊
␊
@ Set K1DB2 for the frequencies that require it␊
@␊
cmp r0, #0x03␊
cmpne r0, #0x04␊
cmpne r0, #0x05␊
cmpne r0, #0x06␊
cmpne r0, #0x07␊
cmpne r0, #0x08␊
cmpne r0, #0x09␊
cmpne r0, #0x0A␊
cmpne r0, #0x0B␊
cmpne r0, #0x0C␊
cmpne r0, #0x10␊
cmpne r0, #0x11␊
cmpne r0, #0x12␊
cmpne r0, #0x13␊
orreq r4, r4, #0x00020000 @ SDCLK[1] = (MemClk)/2 for 03 - 0C @ 10 - 13␊
␊
@␊
@ *Must make MSC0&1 adjustments now for MEMClks > 100MHz.␊
@␊
@ Adjust MSC0 for MemClks > 100 MHz␊
@␊
ldreq r0, [r1, #MSC0_OFFSET]␊
ldreq r3, =0x7F007F00␊
biceq r0, r0, r3 @ clear MSC0[14:12, 11:8] (RRR, RDN)␊
ldreq r3, =0x46004600␊
orreq r0, r0, r3 @ set MSC0[14, 10:9] (doubling RRR, RDN)␊
streq r0, [r1, #MSC0_OFFSET]␊
ldreq r0, [r1, #MSC0_OFFSET] @ read it back to ensure that the data latches␊
␊
@␊
@ Adjust MSC1.LH for MemClks > 100 MHz␊
@␊
ldreq r0, [r1, #MSC1_OFFSET]␊
ldreq r3, =0x7FF0␊
biceq r0, r0, r3 @ clear MSC1[14:12, 11:8, 7:4] (RRR, RDN, RDF)␊
ldreq r3, =0x4880␊
orreq r0, r0, r3 @ set MSC1[14, 11, 7] (doubling RRR, RDN, RDF)␊
streq r0, [r1, #MSC1_OFFSET]␊
ldreq r0, [r1, #MSC1_OFFSET] @ read it back to ensure that the data latches␊
␊
@ @␊
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@␊
#endif␊
/* Note: preserve the mdrefr value in r4 */␊
␊
@<!<!<!<!<!<!<!<!<!<!<! End INSERT 1 <!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<␊
@<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<␊
␊
␉/* ---------------------------------------------------------------- */␊
␉/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */␊
␉/* ---------------------------------------------------------------- */␊
␊
@ write back mdrefr␊
@␊
str r4, [r1, #MDREFR_OFFSET]␊
ldr r4, [r1, #MDREFR_OFFSET]␊
␉/* Initialize SXCNFG register. Assert the enable bits */␊
␊
@ deassert SLFRSH␊
@␊
bic r4, r4, #0x00400000␊
␉/* Write SXMRS to cause an MRS command to all enabled banks of */␊
␉/* synchronous static memory. Note that SXLCR need not be written */␊
␉/* at this time. */␊
␊
@ write back mdrefr␊
@␊
str r4, [r1, #MDREFR_OFFSET]␊
␉/* FIXME: we use async mode for now */␊
␊
@ assert E1PIN␊
@␊
orr r4, r4, #0x00008000␊
␊
@ write back mdrefr␊
@␊
str r4, [r1, #MDREFR_OFFSET]␊
/* ---------------------------------------------------------------- */␊
/* Step 4: Initialize SDRAM */␊
/* ---------------------------------------------------------------- */␊
␊
/* set MDREFR according to user define with exception of a few bits */␊
␊
ldr r4, =CFG_MDREFR_VAL␊
␉orr␉r4,␉r4,␉#(MDREFR_SLFRSH)␊
␉bic␉r4,␉r4,␉#(MDREFR_E1PIN|MDREFR_E0PIN)␊
␉str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */␊
ldr r4, [r1, #MDREFR_OFFSET]␊
nop␊
nop␊
␊
␉/* Step 4b: de-assert MDREFR:SLFRSH. */␊
␊
@****************************************************************************␊
@ Step 4␊
@␊
␉bic␉r4,␉r4,␉#(MDREFR_SLFRSH)␊
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */␊
ldr r4, [r1, #MDREFR_OFFSET]␊
␊
@ fetch platform value of mdcnfg␊
@␊
ldr r2, =CFG_MDCNFG_VAL␊
␊
@ disable all sdram banks␊
@␊
bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)␊
bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)␊
␉/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */␊
␊
@ program banks 0/1 for bus width␊
@␊
bic r2, r2, #MDCNFG_DWID0 @0=32-bit␊
ldr r4, =CFG_MDREFR_VAL␊
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */␊
ldr r4, [r1, #MDREFR_OFFSET]␊
␊
␊
@ write initial value of mdcnfg, w/o enabling sdram banks␊
@␊
str r2, [r1, #MDCNFG_OFFSET]␊
␉/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */␊
␉/* configure but not enable each SDRAM partition pair. */␊
␊
@ ****************************************************************************␊
@ Step 5␊
@␊
␉ldr␉r4,␉=CFG_MDCNFG_VAL␊
␉bic␉r4,␉r4,␉#(MDCNFG_DE0|MDCNFG_DE1)␊
␊
@ pause for 200 uSecs␊
@␊
␉ldr r3, =OSCR @reset the OS Timer Count to zero␊
str r4, [r1, #MDCNFG_OFFSET]␉/* write back MDCNFG */␊
ldr r4, [r1, #MDCNFG_OFFSET]␊
␊
␊
␉/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */␊
␊
␉ldr r3, =OSCR␉␉␉/* reset the OS Timer Count to zero */␊
␉mov r2, #0␊
␉ str r2, [r3]␊
␉ ldr r4, =0x300␉␉␉@really 0x2E1 is about 200usec, so 0x300 should be plenty␊
␉ldr r4, =0x300␉␉␉/* really 0x2E1 is about 200usec, */␊
␉␉␉␉␉/* so 0x300 should be plenty */␊
1:␊
␉ ldr r2, [r3]␊
␉ cmp r4, r2␊
␉ bgt 1b␊
␊
␊
@****************************************************************************␊
@ Step 6␊
@␊
␊
␉ mov r0, #0x78␉␉␉␉ @turn everything off␊
mcr p15, 0, r0, c1, c0, 0␉␉@(caches off, MMU off, etc.)␊
␊
␉/* Step 4f: Trigger a number (usually 8) refresh cycles by */␊
␉/* attempting non-burst read or write accesses to disabled */␊
␉/* SDRAM, as commonly specified in the power up sequence */␊
␉/* documented in SDRAM data sheets. The address(es) used */␊
␉/* for this purpose must not be cacheable. */␊
␊
@ ****************************************************************************␊
@ Step 7␊
@␊
@ Access memory *not yet enabled* for CBR refresh cycles (8)␊
@ - CBR is generated for all banks␊
␉ldr␉r3,␉=CFG_DRAM_BASE␊
␉str␉r2,␉[r3]␊
␉str␉r2,␉[r3]␊
␉str␉r2,␉[r3]␊
␉str␉r2,␉[r3]␊
␉str␉r2,␉[r3]␊
␉str␉r2,␉[r3]␊
␉str␉r2,␉[r3]␊
␉str␉r2,␉[r3]␊
␊
␉ ldr r2, =CFG_DRAM_BASE␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␊
␉/* Step 4g: Write MDCNFG with enable bits asserted */␊
␉/* (MDCNFG:DEx set to 1). */␊
␊
@ ****************************************************************************␊
@ Step 8: NOP (enable dcache if you wanna... we dont)␊
@␊
␊
␊
@ ****************************************************************************␊
@ Step 9␊
@␊
␊
␊
@get memory controller base address␊
@␊
ldr r1, =MEMC_BASE␊
␊
@fetch current mdcnfg value␊
@␊
ldr r3, [r1, #MDCNFG_OFFSET]␊
␊
@enable sdram bank 0 if installed (must do for any populated bank)␊
@␊
orr r3, r3, #MDCNFG_DE0␊
␊
@write back mdcnfg, enabling the sdram bank(s)␊
@␊
␉orr␉r3,␉r3,␉#(MDCNFG_DE0|MDCNFG_DE1)␊
str r3, [r1, #MDCNFG_OFFSET]␊
␊
␉/* Step 4h: Write MDMRS. */␊
␊
@****************************************************************************␊
@ Step 10␊
@␊
␊
@ write mdmrs␊
@␊
ldr r2, =CFG_MDMRS_VAL␊
str r2, [r1, #MDMRS_OFFSET]␊
␊
␊
@****************************************************************************␊
@ Step 11: Final Step␊
@␊
␉/* We are finished with Intel's memory controller initialisation */␊
␊
␊
@INITINTC␊
@********************************************************************␊
@ Disable (mask) all interrupts at the interrupt controller␊
@␊
␉/* ---------------------------------------------------------------- */␊
␉/* Disable (mask) all interrupts at interrupt controller */␊
␉/* ---------------------------------------------------------------- */␊
␊
@ clear the interrupt level register (use IRQ, not FIQ)␊
@␊
mov r1, #0␊
initirqs:␊
␊
mov r1, #0␉␉/* clear int. level register (IRQ, not FIQ) */␊
ldr r2, =ICLR␊
str r1, [r2]␊
␊
@ mask all interrupts at the controller␊
@␊
ldr r2, =ICMR␊
ldr r2, =ICMR␉/* mask all interrupts at the controller */␊
str r1, [r2]␊
␊
␊
@INITCLKS␊
@ ********************************************************************␊
@ Disable the peripheral clocks, and set the core clock␊
@ frequency (hard-coding at 398.12MHz for now).␊
@␊
/* ---------------------------------------------------------------- */␊
␉/* Clock initialisation */␊
/* ---------------------------------------------------------------- */␊
␊
initclks:␊
␊
␉/* Disable the peripheral clocks, and set the core clock frequency */␊
␉/* (hard-coding at 398.12MHz for now). */␊
␊
␉␉@ Turn Off ALL on-chip peripheral clocks for re-configuration␊
␉␉@ *Note: See label 'ENABLECLKS' for the re-enabling␊
␉␉@␊
␉/* Turn Off ALL on-chip peripheral clocks for re-configuration */␊
␉/* Note: See label 'ENABLECLKS' for the re-enabling */␊
ldr r1, =CKEN␊
mov r2, #0␊
str r2, [r1]␊
␊
␊
@ default value in case no valid rotary switch setting is found␊
ldr r2, =(CCCR_L27 | CCCR_M2 | CCCR_N10) @ DEFAULT: {200/200/100}␊
/* default value in case no valid rotary switch setting is found */␊
ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */␊
␊
␊
@... and write the core clock config register␊
@␊
/* ... and write the core clock config register */␊
ldr r1, =CCCR␊
str r2, [r1]␊
␊
/* @ enable the 32Khz oscillator for RTC and PowerManager␊
@␊
#ifdef RTC␊
␉/* enable the 32Khz oscillator for RTC and PowerManager */␊
␊
ldr r1, =OSCC␊
mov r2, #OSCC_OON␊
str r2, [r1]␊
␊
␊
@ NOTE: spin here until OSCC.OOK get set,␊
@ meaning the PLL has settled.␊
@␊
␉/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */␊
␉/* has settled. */␊
60:␊
ldr r2, [r1]␊
ands r2, r2, #1␊
beq 60b␊
*/␊
␊
@OSCC_OON_DONE␊
␊
␊
#ifdef A0_COTULLA␊
@****************************************************************************␊
@ !!! Take care of A0 Errata Sighting #4 --␊
@ after a frequency change, the memory controller must be restarted␊
@␊
␊
@ get memory controller base address␊
ldr r1, =MEMC_BASE␊
␊
@ get the current state of MDREFR␊
@␊
ldr r2, [r1, #MDREFR_OFFSET]␊
␊
@ clear E0PIN, E1PIN␊
@␊
bic r3, r2, #(MDREFR_E0PIN | MDREFR_E1PIN)␊
␊
@ write MDREFR with E0PIN, E1PIN cleared (disable sdclk[0,1])␊
@␊
str r3, [r1, #MDREFR_OFFSET]␊
␊
@ then write MDREFR with E0PIN, E1PIN set (enable sdclk[0,1])␊
@␊
str r2, [r1, #MDREFR_OFFSET]␊
␊
@ get the current state of MDCNFG␊
@␊
ldr r3, [r1, #MDCNFG_OFFSET]␊
␊
@ disable all SDRAM banks␊
@␊
bic r3, r3, #(MDCNFG_DE0 | MDCNFG_DE1)␊
bic r3, r3, #(MDCNFG_DE2 | MDCNFG_DE3)␊
␊
@ write back MDCNFG␊
@␊
ldr r3, [r1, #MDCNFG_OFFSET]␊
␊
␉ @ Access memory not yet enabled for CBR refresh cycles (8)␊
@ - CBR is generated for *all* banks␊
␉ ldr r2, =CFG_DRAM_BASE␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␉ str r2, [r2]␊
␊
@ fetch current mdcnfg value␊
@␊
ldr r3, [r1, #MDCNFG_OFFSET]␊
␊
@ enable sdram bank 0 if installed␊
@␊
orr r3, r3, #MDCNFG_DE0␊
␊
@ write back mdcnfg, enabling the sdram bank(s)␊
@␊
str r3, [r1, #MDCNFG_OFFSET]␊
␊
@ write mdmrs␊
@␊
ldr r2, =CFG_MDMRS_VAL␊
str r2, [r1, #MDMRS_OFFSET]␊
␊
␊
␊
/* @ errata: don't enable auto power-down */␊
@ get current value of mdrefr␊
@ldr r3, [r1, #MDREFR_OFFSET]␊
@ enable auto-power down␊
@orr r3, r3, #MDREFR_APD␊
@write back mdrefr␊
@str r3, [r1, #MDREFR_OFFSET]␊
␊
#endif A0_Cotulla␊
␊
␊
ldr r0, =0x000C0dE3␊
ldr ␉r1, =_LED␊
str ␉r0, [r1] ␉␉/* hex display */␊
␊
@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%␊
@ ^%^%^%^%^%^%^%^%^% above could be replaced by prememLLI ^%^%^%^%^%^%^%^%^%␊
@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%␊
#endif␊
␊
␉/* ---------------------------------------------------------------- */␊
␉/* */␊
/* ---------------------------------------------------------------- */␊
␊
␉/* Save SDRAM size */␊
ldr r1, =DRAM_SIZE␊
␉ str␉ r8, [r1]␊
␊
ldr r0, =0xC0DE0006␊
ldr ␉r1, =_LED␊
str ␉r0, [r1] ␉␉/* hex display */␊
␊
␉/* Interrupt init */␊
␉/* Mask all interrupts */␊
␉/* Interrupt init: Mask all interrupts */␊
ldr␉r0, =ICMR /* enable no sources */␊
␉mov r1, #0␊
str r1, [r0]␊
␊
␉/* FIXME */␊
␊
#define NODEBUG␊
#ifdef NODEBUG␊
␉/*Disable software and data breakpoints */␊
␊
#endif␊
␊
␉ldr r0, =0xBEEF001D␊
ldr ␉r1, =_LED␊
str ␉r0, [r1] ␉␉/* hex display */␊
/* ---------------------------------------------------------------- */␊
␉/* End memsetup */␊
/* ---------------------------------------------------------------- */␊
␊
␉mov␉pc, r10␊
␊
@ End memsetup␊
␊
@ %%%%%%%%%%% Useful subroutines␊
GET_S23:␊
@ This macro will read S23 and return its value in r3␊
@ r2 contains the base address of the Lubbock user registers␊
ldr r2, =FPGA_REGS_BASE_PHYSICAL␊
␊
/*@ read S23's value */␊
ldr r3, [r2, #USER_SWITCHES_OFFSET]␊
␊
@ mask out irrelevant bits␊
and r3, r3, #0x200␊
␊
@ get bit into position 0␊
mov r3, r3, LSR #9␊
␊
mov pc, lr␊
@ End GET_S23␊
␊
␊
GET_S24:␊
@ This macro will read S24 and return its value in r0␊
@ r2 contains the base address of the Lubbock user registers␊
ldr r2, =FPGA_REGS_BASE_PHYSICAL␊
␊
/*@ read S24's value */␊
ldr r0, [r2, #USER_SWITCHES_OFFSET]␊
␊
@ mask out irrelevant bits␊
and r0, r0, #0x100␊
␊
@ get bit into position 0␊
mov r0, r0, LSR #8␊
endmemsetup:␊
␊
mov pc, lr␊
@ End GET_S23␊
␊
␊
GET_S25:␊
@ This macro will read rotary S25 and return its value in r0␊
@ r2 contains the base address of the Lubbock user registers␊
@ read the user switches register␊
ldr r0, [r2, #USER_SWITCHES_OFFSET]␊
␊
@ mask out irrelevant bits␊
and r0, r0, #0xF0␊
␊
mov pc, lr␊
@ End subroutine␊
␊
␊
GET_S26:␊
@ This macro will read rotary S26 and return its value in r3␊
@ r2 contains the base address of the Lubbock user registers␊
@ read the user switches register␊
ldr r3, [r2, #USER_SWITCHES_OFFSET]␊
␊
@ mask out irrelevant bits␊
and r3, r3, #0x0F␊
␊
mov pc, lr␊
@ End subroutine GET_S26␊
␊
␊
board/mpc8260ads/mpc8260ads.c
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/*␊
* (C) Copyright 2001␊
* (C) Copyright 2001-2003␊
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
*␊
* Modified during 2001 by␊
#include <common.h>␊
#include <ioports.h>␊
#include <mpc8260.h>␊
#include <i2c.h>␊
#include <spd.h>␊
␊
/*␊
* I/O Port configuration table␊
␉/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */␊
␉/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */␊
␉/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */␊
␉/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */␊
␉/* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* LED */␊
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */␊
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */␊
␉/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */␊
␉/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */␊
␉/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */␊
␉unsigned long bcsr7;␊
} bcsr_t;␊
␊
void reset_phy(void)␊
void reset_phy (void)␊
{␊
volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;␊
␉volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;␊
␊
/* reset the FEC port */␊
bcsr->bcsr1 &= ~FETH_RST;␊
bcsr->bcsr1 |= FETH_RST;␊
␉/* reset the FEC port */␊
␉bcsr->bcsr1 &= ~FETH_RST;␊
␉bcsr->bcsr1 |= FETH_RST;␊
}␊
␊
␊
int board_pre_init (void)␊
{␊
volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;␊
bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;␊
␉volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;␊
␊
return 0;␊
␉bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;␊
␊
␉return 0;␊
}␊
␊
long int initdram(int board_type)␊
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)␊
␊
long int initdram (int board_type)␊
{␊
volatile immap_t *immap = (immap_t *)CFG_IMMR;␊
volatile memctl8260_t *memctl = &immap->im_memctl;␊
volatile uchar *ramaddr,␊
c = 0xff;␊
int i;␊
␉volatile immap_t *immap = (immap_t *) CFG_IMMR;␊
␉volatile memctl8260_t *memctl = &immap->im_memctl;␊
␉volatile uchar *ramaddr, c = 0xff;␊
␊
␉/* Initialisation is for 16MB DIMM the board is shipped with */␊
␉long int msize = 16;␊
␉uint or = 0xFF000CA0;␊
␉uint psdmr = CFG_PSDMR;␊
␉uint psrt = CFG_PSRT;␊
␊
␉int i;␊
␊
#ifndef CFG_RAMBOOT␊
immap->im_siu_conf.sc_ppc_acr = 0x00000002;␊
immap->im_siu_conf.sc_ppc_alrh = 0x01267893;␊
immap->im_siu_conf.sc_tescr1 = 0x00004000;␊
␊
/* init local sdram, bank 4 */␊
memctl->memc_lsrt = 0x00000010;␊
memctl->memc_or4 = 0xFFC01480;␊
memctl->memc_br4 = 0x04001861;␊
memctl->memc_lsdmr = 0x2886A522;␊
ramaddr = (uchar *)CFG_LSDRAM_BASE;␊
*ramaddr = c;␊
memctl->memc_lsdmr = 0x0886A522;␊
for( i = 0; i < 8; i++ ) {␊
*ramaddr = c;␊
}␊
memctl->memc_lsdmr = 0x1886A522;␊
*ramaddr = c;␊
memctl->memc_lsdmr = 0x4086A522;␊
␊
/* init sdram dimm */␊
ramaddr = (uchar *)CFG_SDRAM_BASE;␊
memctl->memc_psrt = 0x00000010;␊
immap->im_memctl.memc_or2 = 0xFF000CA0;␊
immap->im_memctl.memc_br2 = 0x00000041;␊
memctl->memc_psdmr = 0x296EB452;␊
*ramaddr = c;␊
memctl->memc_psdmr = 0x096EB452;␊
for (i = 0; i < 8; i++)␊
*ramaddr = c;␊
␊
memctl->memc_psdmr = 0x196EB452;␊
*ramaddr = c;␊
memctl->memc_psdmr = 0x416EB452;␊
*ramaddr = c;␊
␉immap->im_siu_conf.sc_ppc_acr = 0x00000002;␊
␉immap->im_siu_conf.sc_ppc_alrh = 0x01267893;␊
␉immap->im_siu_conf.sc_tescr1 = 0x00004000;␊
␊
␉memctl->memc_mptpr = CFG_MPTPR;␊
␉/* init local sdram, bank 4 */␊
␉memctl->memc_lsrt = 0x00000010;␊
␉memctl->memc_or4 = 0xFFC01480;␊
␉memctl->memc_br4 = 0x04001861;␊
␉memctl->memc_lsdmr = 0x2886A522;␊
␉ramaddr = (uchar *) CFG_LSDRAM_BASE;␊
␉*ramaddr = c;␊
␉memctl->memc_lsdmr = 0x0886A522;␊
␉for (i = 0; i < 8; i++) {␊
␉␉*ramaddr = c;␊
␉}␊
␉memctl->memc_lsdmr = 0x1886A522;␊
␉*ramaddr = c;␊
␉memctl->memc_lsdmr = 0x4086A522;␊
␊
␉/* init sdram dimm */␊
#ifdef CONFIG_SPD_EEPROM␊
␉{␊
␉␉spd_eeprom_t spd;␊
␉␉uint pbi, bsel, rowst, lsb, tmp;␊
␊
␉␉i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));␊
␊
␉␉/* Bank-based interleaving is not supported for physical bank␊
␉␉ sizes greater than 128MB which is encoded as 0x20 in SPD␊
␉␉ */␊
␉␉pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;␊
␉␉msize = spd.nrows * (4 * spd.row_dens);␉/* Mixed size not supported */␊
␉␉or = ~(msize - 1) << 20;␉/* SDAM */␊
␉␉switch (spd.nbanks) {␉/* BPD */␊
␉␉case 2:␊
␉␉␉bsel = 1;␊
␉␉␉break;␊
␉␉case 4:␊
␉␉␉bsel = 2;␊
␉␉␉or |= 0x00002000;␊
␉␉␉break;␊
␉␉case 8:␊
␉␉␉bsel = 3;␊
␉␉␉or |= 0x00004000;␊
␉␉␉break;␊
␉␉}␊
␉␉lsb = 3;␉/* For 64-bit port, lsb is 3 bits */␊
␊
␉␉if (pbi) {␉/* Bus partition depends on interleaving */␊
␉␉␉rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);␊
␉␉␉or |= (rowst << 9);␉/* ROWST */␊
␉␉} else {␊
␉␉␉rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);␊
␉␉␉or |= ((rowst * 2 - 12) << 9);␉/* ROWST */␊
␉␉}␊
␉␉or |= ((spd.nrow_addr - 9) << 6);␉/* NUMR */␊
␊
␉␉psdmr = (pbi << 31);␉/* PBI */␊
␉␉/* Bus multiplexing parameters */␊
␉␉tmp = 32 - (lsb + spd.nrow_addr);␉/* Tables 10-19 and 10-20 */␊
␉␉psdmr |= ((tmp - (rowst - 5) - 13) << 24);␉/* SDAM */␊
␉␉psdmr |= ((tmp - 3 - 12) << 21);␉/* BSMA */␊
␊
␉␉tmp = (31 - lsb - 10) - tmp;␊
␉␉/* Pin connected to SDA10 is (31 - lsb - 10).␊
␉␉ rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),␊
␉␉ so (rowst + tmp) alternates with AP.␊
␉␉ */␊
␉␉if (pbi)␉␉␉␉/* Table 10-7 */␊
␉␉␉psdmr |= ((10 - (rowst + tmp)) << 18);␉/* SDA10 */␊
␉␉else␊
␉␉␉psdmr |= ((12 - (rowst + tmp)) << 18);␉/* SDA10 */␊
␊
␉␉/* SDRAM device-specific parameters */␊
␉␉tmp = ns2clk (70);␉/* Refresh recovery is not in SPD, so assume 70ns */␊
␉␉switch (tmp) {␉␉/* RFRC */␊
␉␉case 1:␊
␉␉case 2:␊
␉␉␉psdmr |= (1 << 15);␊
␉␉␉break;␊
␉␉case 3:␊
␉␉case 4:␊
␉␉case 5:␊
␉␉case 6:␊
␉␉case 7:␊
␉␉case 8:␊
␉␉␉psdmr |= ((tmp - 2) << 15);␊
␉␉␉break;␊
␉␉default:␊
␉␉␉psdmr |= (7 << 15);␊
␉␉}␊
␉␉psdmr |= (ns2clk (spd.trp) % 8 << 12);␉/* PRETOACT */␊
␉␉psdmr |= (ns2clk (spd.trcd) % 8 << 9);␉/* ACTTORW */␊
␉␉/* BL=0 because for 64-bit SDRAM burst length must be 4 */␊
␉␉/* LDOTOPRE ??? */␊
␉␉for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)␊
␉␉␉tmp >>= 1;␊
␉␉switch (i) {␉␉␉/* WRC */␊
␉␉case 0:␊
␉␉case 1:␊
␉␉␉psdmr |= (1 << 4);␊
␉␉␉break;␊
␉␉case 2:␊
␉␉case 3:␊
␉␉␉psdmr |= (i << 4);␊
␉␉␉break;␊
␉␉}␊
␉␉/* EAMUX=0 - no external address multiplexing */␊
␉␉/* BUFCMD=0 - no external buffers */␊
␉␉for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)␊
␉␉␉tmp >>= 1;␊
␉␉psdmr |= i;␉␉␉␉/* CL */␊
␊
␉␉switch (spd.refresh & 0x7F) {␊
␉␉case 1:␊
␉␉␉tmp = 3900;␊
␉␉␉break;␊
␉␉case 2:␊
␉␉␉tmp = 7800;␊
␉␉␉break;␊
␉␉case 3:␊
␉␉␉tmp = 31300;␊
␉␉␉break;␊
␉␉case 4:␊
␉␉␉tmp = 62500;␊
␉␉␉break;␊
␉␉case 5:␊
␉␉␉tmp = 125000;␊
␉␉␉break;␊
␉␉default:␊
␉␉␉tmp = 15625;␊
␉␉}␊
␉␉psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *␊
␉␉␉␉ ((memctl->memc_mptpr >> 8) + 1)) - 1;␊
#ifdef SPD_DEBUG␊
␉␉printf ("\nDIMM type: %-18.18s\n", spd.mpart);␊
␉␉printf ("SPD size: %d\n", spd.info_size);␊
␉␉printf ("EEPROM size: %d\n", 1 << spd.chip_size);␊
␉␉printf ("Memory type: %d\n", spd.mem_type);␊
␉␉printf ("Row addr: %d\n", spd.nrow_addr);␊
␉␉printf ("Column addr: %d\n", spd.ncol_addr);␊
␉␉printf ("# of rows: %d\n", spd.nrows);␊
␉␉printf ("Row density: %d\n", spd.row_dens);␊
␉␉printf ("# of banks: %d\n", spd.nbanks);␊
␉␉printf ("Data width: %d\n",␊
␉␉␉␉256 * spd.dataw_msb + spd.dataw_lsb);␊
␉␉printf ("Chip width: %d\n", spd.primw);␊
␉␉printf ("Refresh rate: %02X\n", spd.refresh);␊
␉␉printf ("CAS latencies: %02X\n", spd.cas_lat);␊
␉␉printf ("Write latencies: %02X\n", spd.write_lat);␊
␉␉printf ("tRP: %d\n", spd.trp);␊
␉␉printf ("tRCD: %d\n", spd.trcd);␊
␊
␉␉printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);␊
#endif /* SPD_DEBUG */␊
␉}␊
#endif /* CONFIG_SPD_EEPROM */␊
␉memctl->memc_psrt = psrt;␊
␉memctl->memc_or2 = or;␊
␉memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;␊
␉ramaddr = (uchar *) CFG_SDRAM_BASE;␊
␉memctl->memc_psdmr = psdmr | 0x28000000;␉/* Precharge all banks */␊
␉*ramaddr = c;␊
␉memctl->memc_psdmr = psdmr | 0x08000000;␉/* CBR refresh */␊
␉for (i = 0; i < 8; i++)␊
␉␉*ramaddr = c;␊
␊
␉memctl->memc_psdmr = psdmr | 0x18000000;␉/* Mode Register write */␊
␉*ramaddr = c;␊
␉memctl->memc_psdmr = psdmr | 0x40000000;␉/* Refresh enable */␊
␉*ramaddr = c;␊
#endif␊
␊
/* return total ram size of simm */␊
return (16 * 1024 * 1024);␊
␉/* return total ram size of DIMM */␊
␉return (msize * 1024 * 1024);␊
}␊
␊
int checkboard(void)␊
int checkboard (void)␊
{␊
puts ("Board: Motorola MPC8260ADS\n");␊
return 0;␊
␉puts ("Board: Motorola MPC8260ADS\n");␊
␉return 0;␊
}␊
␊
board/mpc8266ads/Makefile
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#␊
# (C) Copyright 2001␊
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
#␊
# See file CREDITS for list of people who contributed to this␊
# project.␊
#␊
# This program is free software; you can redistribute it and/or␊
# modify it under the terms of the GNU General Public License as␊
# published by the Free Software Foundation; either version 2 of␊
# the License, or (at your option) any later version.␊
#␊
# This program is distributed in the hope that it will be useful,␊
# but WITHOUT ANY WARRANTY; without even the implied warranty of␊
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
# GNU General Public License for more details.␊
#␊
# You should have received a copy of the GNU General Public License␊
# along with this program; if not, write to the Free Software␊
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
# MA 02111-1307 USA␊
#␊
␊
include $(TOPDIR)/config.mk␊
␊
LIB␉= lib$(BOARD).a␊
␊
OBJS␉:= $(BOARD).o flash.o␊
␊
$(LIB):␉$(OBJS) $(SOBJS)␊
␉$(AR) crv $@ $^␊
␊
clean:␊
␉rm -f $(SOBJS) $(OBJS)␊
␊
distclean:␉clean␊
␉rm -f $(LIB) core *.bak .depend␊
␊
#########################################################################␊
␊
.depend:␉Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)␊
␉␉$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@␊
␊
-include .depend␊
␊
#########################################################################␊
board/mpc8266ads/config.mk
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#␊
# (C) Copyright 2001␊
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
#␊
# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com␊
#␊
# See file CREDITS for list of people who contributed to this␊
# project.␊
#␊
# This program is free software; you can redistribute it and/or␊
# modify it under the terms of the GNU General Public License as␊
# published by the Free Software Foundation; either version 2 of␊
# the License, or (at your option) any later version.␊
#␊
# This program is distributed in the hope that it will be useful,␊
# but WITHOUT ANY WARRANTY; without even the implied warranty of␊
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
# GNU General Public License for more details.␊
#␊
# You should have received a copy of the GNU General Public License␊
# along with this program; if not, write to the Free Software␊
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
# MA 02111-1307 USA␊
#␊
␊
#␊
# mpc8260ads board␊
#␊
␊
TEXT_BASE = 0xfff00000␊
␊
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board␊
board/mpc8266ads/flash.c
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/*␊
* (C) Copyright 2000, 2001␊
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
*␊
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com␊
* Add support the Sharp chips on the mpc8260ads.␊
* I started with board/ip860/flash.c and made changes I found in␊
* the MTD project by David Schleef.␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
#include <common.h>␊
␊
␊
flash_info_t␉flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips␉*/␊
␊
#if defined(CFG_ENV_IS_IN_FLASH)␊
# ifndef CFG_ENV_ADDR␊
# define CFG_ENV_ADDR␉(CFG_FLASH_BASE + CFG_ENV_OFFSET)␊
# endif␊
# ifndef CFG_ENV_SIZE␊
# define CFG_ENV_SIZE␉CFG_ENV_SECT_SIZE␊
# endif␊
# ifndef CFG_ENV_SECT_SIZE␊
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE␊
# endif␊
#endif␊
␊
/*-----------------------------------------------------------------------␊
* Functions␊
*/␊
static ulong flash_get_size (vu_long *addr, flash_info_t *info);␊
static int write_word (flash_info_t *info, ulong dest, ulong data);␊
static int clear_block_lock_bit(vu_long * addr);␊
␊
/*-----------------------------------------------------------------------␊
*/␊
␊
unsigned long flash_init (void)␊
{␊
#ifndef CONFIG_MPC8260ADS␊
␉volatile immap_t␉*immap = (immap_t *)CFG_IMMR;␊
␉volatile memctl8xx_t␉*memctl = &immap->im_memctl;␊
␉volatile ip860_bcsr_t␉*bcsr = (ip860_bcsr_t *)BCSR_BASE;␊
#endif␊
␉unsigned long size;␊
␉int i;␊
␊
␉/* Init: enable write,␊
␉ * or we cannot even write flash commands␊
␉ */␊
#ifndef CONFIG_MPC8260ADS␊
␉bcsr->bd_ctrl |= BD_CTRL_FLWE;␊
#endif␊
␊
␊
␉for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {␊
␉␉flash_info[i].flash_id = FLASH_UNKNOWN;␊
␊
␉␉/* set the default sector offset */␊
␉}␊
␊
␉/* Static FLASH Bank configuration here - FIXME XXX */␊
␊
␉size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);␊
␊
␉if (flash_info[0].flash_id == FLASH_UNKNOWN) {␊
␉␉printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",␊
␉␉␉size, size<<20);␊
␉}␊
␊
#ifndef CONFIG_MPC8260ADS␊
␉/* Remap FLASH according to real size */␊
␉memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);␊
␉memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |␊
␉␉␉␉(memctl->memc_br1 & ~(BR_BA_MSK));␊
#endif␊
␉/* Re-do sizing to get full correct info */␊
␉size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);␊
␊
␉flash_info[0].size = size;␊
␊
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE␊
␉/* monitor protection ON by default */␊
␉flash_protect(FLAG_PROTECT_SET,␊
␉␉ CFG_MONITOR_BASE,␊
␉␉ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,␊
␉␉ &flash_info[0]);␊
#endif␊
␊
#ifdef␉CFG_ENV_IS_IN_FLASH␊
␉/* ENV protection ON by default */␊
␉flash_protect(FLAG_PROTECT_SET,␊
␉␉ CFG_ENV_ADDR,␊
␉␉ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,␊
␉␉ &flash_info[0]);␊
#endif␊
␉return (size);␊
}␊
␊
/*-----------------------------------------------------------------------␊
*/␊
void flash_print_info (flash_info_t *info)␊
{␊
␉int i;␊
␊
␉if (info->flash_id == FLASH_UNKNOWN) {␊
␉␉printf ("missing or unknown FLASH type\n");␊
␉␉return;␊
␉}␊
␊
␉switch (info->flash_id & FLASH_VENDMASK) {␊
␉case FLASH_MAN_INTEL:␉printf ("Intel ");␉␉break;␊
␉case FLASH_MAN_SHARP: printf ("Sharp ");␉␉break;␊
␉default:␉␉printf ("Unknown Vendor ");␉break;␊
␉}␊
␊
␉switch (info->flash_id & FLASH_TYPEMASK) {␊
␉case FLASH_28F016SV:␉printf ("28F016SV (16 Mbit, 32 x 64k)\n");␊
␉␉␉␉break;␊
␉case FLASH_28F160S3:␉printf ("28F160S3 (16 Mbit, 32 x 512K)\n");␊
␉␉␉␉break;␊
␉case FLASH_28F320S3:␉printf ("28F320S3 (32 Mbit, 64 x 512K)\n");␊
␉␉␉␉break;␊
␉case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");␊
␉␉␉␉break;␊
␉default:␉␉printf ("Unknown Chip Type\n");␊
␉␉␉␉break;␊
␉}␊
␊
␉printf (" Size: %ld MB in %d Sectors\n",␊
␉␉info->size >> 20, info->sector_count);␊
␊
␉printf (" Sector Start Addresses:");␊
␉for (i=0; i<info->sector_count; ++i) {␊
␉␉if ((i % 5) == 0)␊
␉␉␉printf ("\n ");␊
␉␉printf (" %08lX%s",␊
␉␉␉info->start[i],␊
␉␉␉info->protect[i] ? " (RO)" : " "␊
␉␉);␊
␉}␊
␉printf ("\n");␊
}␊
␊
/*-----------------------------------------------------------------------␊
*/␊
␊
␊
/*-----------------------------------------------------------------------␊
*/␊
␊
/*␊
* The following code cannot be run from FLASH!␊
*/␊
␊
static ulong flash_get_size (vu_long *addr, flash_info_t *info)␊
{␊
␉short i;␊
␉ulong value;␊
␉ulong base = (ulong)addr;␊
␉ulong sector_offset;␊
␊
␉/* Write "Intelligent Identifier" command: read Manufacturer ID */␊
␉*addr = 0x90909090;␊
␊
␉value = addr[0] & 0x00FF00FF;␊
␉switch (value) {␊
␉case MT_MANUFACT:␉/* SHARP, MT or => Intel */␊
␉case INTEL_ALT_MANU:␊
␉␉info->flash_id = FLASH_MAN_INTEL;␊
␉␉break;␊
␉default:␊
␉␉printf("unknown manufacturer: %x\n", (unsigned int)value);␊
␉␉info->flash_id = FLASH_UNKNOWN;␊
␉␉info->sector_count = 0;␊
␉␉info->size = 0;␊
␉␉return (0);␉␉␉/* no or unknown flash␉*/␊
␉}␊
␊
␉value = addr[1];␉␉␉/* device ID␉␉*/␊
␊
␉switch (value) {␊
␉case (INTEL_ID_28F016S):␊
␉␉info->flash_id += FLASH_28F016SV;␊
␉␉info->sector_count = 32;␊
␉␉info->size = 0x00400000;␊
␉␉sector_offset = 0x20000;␊
␉␉break;␉␉␉␉/* => 2x2 MB␉␉*/␊
␊
␉case (INTEL_ID_28F160S3):␊
␉␉info->flash_id += FLASH_28F160S3;␊
␉␉info->sector_count = 32;␊
␉␉info->size = 0x00400000;␊
␉␉sector_offset = 0x20000;␊
␉␉break;␉␉␉␉/* => 2x2 MB␉␉*/␊
␊
␉case (INTEL_ID_28F320S3):␊
␉␉info->flash_id += FLASH_28F320S3;␊
␉␉info->sector_count = 64;␊
␉␉info->size = 0x00800000;␊
␉␉sector_offset = 0x20000;␊
␉␉break;␉␉␉␉/* => 2x4 MB␉␉*/␊
␊
␉case SHARP_ID_28F016SCL:␊
␉case SHARP_ID_28F016SCZ:␊
␉␉info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;␊
␉␉info->sector_count = 32;␊
␉␉info->size = 0x00800000;␊
␉␉sector_offset = 0x40000;␊
␉␉break;␉␉␉␉/* => 4x2 MB␉␉*/␊
␊
␊
␉default:␊
␉␉info->flash_id = FLASH_UNKNOWN;␊
␉␉return (0);␉␉␉/* => no or unknown flash */␊
␊
␉}␊
␊
␉/* set up sector start address table */␊
␉for (i = 0; i < info->sector_count; i++) {␊
␉␉info->start[i] = base;␊
␉␉base += sector_offset;␊
␉␉/* don't know how to check sector protection */␊
␉␉info->protect[i] = 0;␊
␉}␊
␊
␉/*␊
␉ * Prevent writes to uninitialized FLASH.␊
␉ */␊
␉if (info->flash_id != FLASH_UNKNOWN) {␊
␉␉addr = (vu_long *)info->start[0];␊
␊
␉␉*addr = 0xFFFFFF;␉/* reset bank to read array mode */␊
␉}␊
␊
␉return (info->size);␊
}␊
␊
␊
/*-----------------------------------------------------------------------␊
*/␊
␊
int␉flash_erase (flash_info_t *info, int s_first, int s_last)␊
{␊
␉int flag, prot, sect;␊
␉ulong start, now, last;␊
␊
␉if ((s_first < 0) || (s_first > s_last)) {␊
␉␉if (info->flash_id == FLASH_UNKNOWN) {␊
␉␉␉printf ("- missing\n");␊
␉␉} else {␊
␉␉␉printf ("- no sectors to erase\n");␊
␉␉}␊
␉␉return 1;␊
␉}␊
␊
␉if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)␊
␉ && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {␊
␉␉printf ("Can't erase unknown flash type %08lx - aborted\n",␊
␉␉␉info->flash_id);␊
␉␉return 1;␊
␉}␊
␊
␉prot = 0;␊
␉for (sect=s_first; sect<=s_last; ++sect) {␊
␉␉if (info->protect[sect]) {␊
␉␉␉prot++;␊
␉␉}␊
␉}␊
␊
␉if (prot) {␊
␉␉printf ("- Warning: %d protected sectors will not be erased!\n",␊
␉␉␉prot);␊
␉} else {␊
␉␉printf ("\n");␊
␉}␊
␊
␉/* Make Sure Block Lock Bit is not set. */␊
␉if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){␊
␉␉return 1;␊
␉}␊
␊
␊
␉/* Start erase on unprotected sectors */␊
␉for (sect = s_first; sect<=s_last; sect++) {␊
␉␉if (info->protect[sect] == 0) {␉/* not protected */␊
␉␉␉vu_long *addr = (vu_long *)(info->start[sect]);␊
␊
␉␉␉last = start = get_timer (0);␊
␊
␉␉␉/* Disable interrupts which might cause a timeout here */␊
␉␉␉flag = disable_interrupts();␊
␊
␉␉␉/* Reset Array */␊
␉␉␉*addr = 0xffffffff;␊
␉␉␉/* Clear Status Register */␊
␉␉␉*addr = 0x50505050;␊
␉␉␉/* Single Block Erase Command */␊
␉␉␉*addr = 0x20202020;␊
␉␉␉/* Confirm */␊
␉␉␉*addr = 0xD0D0D0D0;␊
␊
␉␉␉if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {␊
␉␉␉ /* Resume Command, as per errata update */␊
␉␉␉ *addr = 0xD0D0D0D0;␊
␉␉␉}␊
␊
␉␉␉/* re-enable interrupts if necessary */␊
␉␉␉if (flag)␊
␉␉␉␉enable_interrupts();␊
␊
␉␉␉/* wait at least 80us - let's wait 1 ms */␊
␉␉␉udelay (1000);␊
␉␉␉while ((*addr & 0x80808080) != 0x80808080) {␊
␉␉␉␉if(*addr & 0x20202020){␊
␉␉␉␉␉printf("Error in Block Erase - Lock Bit may be set!\n");␊
␉␉␉␉␉printf("Status Register = 0x%X\n", (uint)*addr);␊
␉␉␉␉␉*addr = 0xFFFFFFFF;␉/* reset bank */␊
␉␉␉␉␉return 1;␊
␉␉␉␉}␊
␉␉␉␉if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {␊
␉␉␉␉␉printf ("Timeout\n");␊
␉␉␉␉␉*addr = 0xFFFFFFFF;␉/* reset bank */␊
␉␉␉␉␉return 1;␊
␉␉␉␉}␊
␉␉␉␉/* show that we're waiting */␊
␉␉␉␉if ((now - last) > 1000) {␉/* every second */␊
␉␉␉␉␉putc ('.');␊
␉␉␉␉␉last = now;␊
␉␉␉␉}␊
␉␉␉}␊
␊
␉␉␉/* reset to read mode */␊
␉␉␉*addr = 0xFFFFFFFF;␊
␉␉}␊
␉}␊
␊
␉printf (" done\n");␊
␉return 0;␊
}␊
␊
/*-----------------------------------------------------------------------␊
* Copy memory to flash, returns:␊
* 0 - OK␊
* 1 - write timeout␊
* 2 - Flash not erased␊
*/␊
␊
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)␊
{␊
␉ulong cp, wp, data;␊
␉int i, l, rc;␊
␊
␉wp = (addr & ~3);␉/* get lower word aligned address */␊
␊
␉/*␊
␉ * handle unaligned start bytes␊
␉ */␊
␉if ((l = addr - wp) != 0) {␊
␉␉data = 0;␊
␉␉for (i=0, cp=wp; i<l; ++i, ++cp) {␊
␉␉␉data = (data << 8) | (*(uchar *)cp);␊
␉␉}␊
␉␉for (; i<4 && cnt>0; ++i) {␊
␉␉␉data = (data << 8) | *src++;␊
␉␉␉--cnt;␊
␉␉␉++cp;␊
␉␉}␊
␉␉for (; cnt==0 && i<4; ++i, ++cp) {␊
␉␉␉data = (data << 8) | (*(uchar *)cp);␊
␉␉}␊
␊
␉␉if ((rc = write_word(info, wp, data)) != 0) {␊
␉␉␉return (rc);␊
␉␉}␊
␉␉wp += 4;␊
␉}␊
␊
␉/*␊
␉ * handle word aligned part␊
␉ */␊
␉while (cnt >= 4) {␊
␉␉data = 0;␊
␉␉for (i=0; i<4; ++i) {␊
␉␉␉data = (data << 8) | *src++;␊
␉␉}␊
␉␉if ((rc = write_word(info, wp, data)) != 0) {␊
␉␉␉return (rc);␊
␉␉}␊
␉␉wp += 4;␊
␉␉cnt -= 4;␊
␉}␊
␊
␉if (cnt == 0) {␊
␉␉return (0);␊
␉}␊
␊
␉/*␊
␉ * handle unaligned tail bytes␊
␉ */␊
␉data = 0;␊
␉for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {␊
␉␉data = (data << 8) | *src++;␊
␉␉--cnt;␊
␉}␊
␉for (; i<4; ++i, ++cp) {␊
␉␉data = (data << 8) | (*(uchar *)cp);␊
␉}␊
␊
␉return (write_word(info, wp, data));␊
}␊
␊
/*-----------------------------------------------------------------------␊
* Write a word to Flash, returns:␊
* 0 - OK␊
* 1 - write timeout␊
* 2 - Flash not erased␊
*/␊
static int write_word (flash_info_t *info, ulong dest, ulong data)␊
{␊
␉vu_long *addr = (vu_long *)dest;␊
␉ulong start, csr;␊
␉int flag;␊
␊
␉/* Check if Flash is (sufficiently) erased */␊
␉if ((*addr & data) != data) {␊
␉␉return (2);␊
␉}␊
␉/* Disable interrupts which might cause a timeout here */␊
␉flag = disable_interrupts();␊
␊
␉/* Write Command */␊
␉*addr = 0x10101010;␊
␊
␉/* Write Data */␊
␉*addr = data;␊
␊
␉/* re-enable interrupts if necessary */␊
␉if (flag)␊
␉␉enable_interrupts();␊
␊
␉/* data polling for D7 */␊
␉start = get_timer (0);␊
␉flag = 0;␊
␉while (((csr = *addr) & 0x80808080) != 0x80808080) {␊
␉␉if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {␊
␉␉␉flag = 1;␊
␉␉␉break;␊
␉␉}␊
␉}␊
␉if (csr & 0x40404040) {␊
␉␉printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);␊
␉␉flag = 1;␊
␉}␊
␊
␉/* Clear Status Registers Command */␊
␉*addr = 0x50505050;␊
␉/* Reset to read array mode */␊
␉*addr = 0xFFFFFFFF;␊
␊
␉return (flag);␊
}␊
␊
/*-----------------------------------------------------------------------␊
* Clear Block Lock Bit, returns:␊
* 0 - OK␊
* 1 - Timeout␊
*/␊
␊
static int clear_block_lock_bit(vu_long * addr)␊
{␊
␉ulong start, now;␊
␊
␉/* Reset Array */␊
␉*addr = 0xffffffff;␊
␉/* Clear Status Register */␊
␉*addr = 0x50505050;␊
␊
␉*addr = 0x60606060;␊
␉*addr = 0xd0d0d0d0;␊
␊
␉start = get_timer (0);␊
␉while(*addr != 0x80808080){␊
␉␉if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {␊
␉␉␉printf ("Timeout on clearing Block Lock Bit\n");␊
␉␉␉*addr = 0xFFFFFFFF;␉/* reset bank */␊
␉␉␉return 1;␊
␉␉}␊
␉}␊
␉return 0;␊
}␊
board/mpc8266ads/mpc8266ads.c
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/*␊
* (C) Copyright 2001␊
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
*␊
* Modified during 2001 by␊
* Advanced Communications Technologies (Australia) Pty. Ltd.␊
* Howard Walker, Tuong Vu-Dinh␊
*␊
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com␊
* Added support for the 16M dram simm on the 8260ads boards␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
#include <common.h>␊
#include <ioports.h>␊
#include <i2c.h>␊
#include <mpc8260.h>␊
␊
/*␊
* PBI Page Based Interleaving␊
* PSDMR_PBI page based interleaving␊
* 0 bank based interleaving␊
* External Address Multiplexing (EAMUX) adds a clock to address cycles␊
* (this can help with marginal board layouts)␊
* PSDMR_EAMUX adds a clock␊
* 0 no extra clock␊
* Buffer Command (BUFCMD) adds a clock to command cycles.␊
* PSDMR_BUFCMD adds a clock␊
* 0 no extra clock␊
*/␊
#define CONFIG_PBI␉␉0␊
#define PESSIMISTIC_SDRAM␉0␊
#define EAMUX␉␉␉0␉/* EST requires EAMUX */␊
#define BUFCMD␉␉␉0␊
␊
␊
/*␊
* I/O Port configuration table␊
*␊
* if conf is 1, then that port pin will be configured at boot time␊
* according to the five values podr/pdir/ppar/psor/pdat for that entry␊
*/␊
␊
const iop_conf_t iop_conf_tab[4][32] = {␊
␊
/* Port A configuration */␊
{␉/*␉ conf ppar psor pdir podr pdat */␊
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */␊
␉/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */␊
␉/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */␊
␉/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */␊
␉/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */␊
␉/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */␊
␉/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */␊
␉/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */␊
␉/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */␊
␉/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */␊
␉/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */␊
␉/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */␊
␉/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */␊
␉/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */␊
␉/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */␊
␉/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */␊
␉/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */␊
␉/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */␊
␉/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */␊
␉/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */␊
␉/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */␊
␉/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */␊
␉/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */␊
␉/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */␊
␉/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */␊
␉/* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */␊
␉/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */␊
␉/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */␊
␉/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */␊
␉/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */␊
␉/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */␊
␉/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */␊
},␊
␊
/* Port B configuration */␊
{ /*␉ conf ppar psor pdir podr pdat */␊
␉/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */␊
␉/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */␊
␉/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */␊
␉/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */␊
␉/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */␊
␉/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */␊
␉/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */␊
␉/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */␊
␉/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */␊
␉/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */␊
␉/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */␊
␉/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */␊
␉/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */␊
␉/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */␊
␉/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */␊
␉/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */␊
␉/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */␊
␉/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */␊
␉/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */␊
␉/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */␊
␉/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */␊
␉/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */␊
␉/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */␊
␉/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */␊
␉/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */␊
␉/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */␊
␉/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */␊
␉/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */␊
␉/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */␊
},␊
␊
/* Port C */␊
{ /*␉ conf ppar psor pdir podr pdat */␊
␉/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */␊
␉/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */␊
␉/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */␊
␉/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */␊
␉/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */␊
␉/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */␊
␉/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */␊
␉/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */␊
␉/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */␊
␉/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */␊
␉/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */␊
␉/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */␊
␉/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */␊
␉/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */␊
␉/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */␊
␉/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */␊
␉/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */␊
␉/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */␊
␉/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */␊
␉/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */␊
␉/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */␊
␉/* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDC */␊
␉/* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */␊
␉/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */␊
␉/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */␊
␉/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */␊
␉/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */␊
␉/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */␊
␉/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */␊
␉/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */␊
␉/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */␊
␉/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */␊
},␊
␊
/* Port D */␊
{ /*␉ conf ppar psor pdir podr pdat */␊
␉/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */␊
␉/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */␊
␉/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */␊
␉/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */␊
␉/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */␊
␉/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */␊
␉/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */␊
␉/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */␊
␉/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */␊
␉/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */␊
␉/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */␊
␉/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */␊
␉/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */␊
␉/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */␊
␉/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */␊
␉/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */␊
␉/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */␊
␉/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */␊
␉/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */␊
␉/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */␊
␉/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */␊
␉/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */␊
␉/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */␊
␉/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */␊
␉/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */␊
␉/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */␊
␉/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */␊
␉/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */␊
␉/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */␊
}␊
};␊
␊
typedef struct bscr_ {␊
␉unsigned long bcsr0;␊
␉unsigned long bcsr1;␊
␉unsigned long bcsr2;␊
␉unsigned long bcsr3;␊
␉unsigned long bcsr4;␊
␉unsigned long bcsr5;␊
␉unsigned long bcsr6;␊
␉unsigned long bcsr7;␊
} bcsr_t;␊
␊
void reset_phy(void)␊
{␊
volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;␊
␊
/* reset the FEC port */␊
bcsr->bcsr1 &= ~FETH_RST;␊
bcsr->bcsr1 |= FETH_RST;␊
}␊
␊
␊
int board_pre_init (void)␊
{␊
volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;␊
bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;␊
␊
return 0;␊
}␊
␊
int checkboard(void)␊
{␊
puts ("Board: Motorola MPC8266ADS\n");␊
return 0;␊
}␊
␊
long int initdram(int board_type)␊
{␊
␉/* Autoinit part stolen from board/sacsng/sacsng.c */␊
volatile immap_t *immap = (immap_t *)CFG_IMMR;␊
volatile memctl8260_t *memctl = &immap->im_memctl;␊
volatile uchar c = 0xff;␊
volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);␊
uint psdmr = CFG_PSDMR;␊
int i;␊
␊
uint psrt = 14;␉␉␉␉␉/* for no SPD */␊
uint chipselects = 1;␉␉␉␉/* for no SPD */␊
uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024;␉/* for no SPD */␊
uint or = CFG_OR2_PRELIM;␉␉␉␉/* for no SPD */␊
uint data_width;␊
uint rows;␊
uint banks;␊
uint cols;␊
uint caslatency;␊
uint width;␊
uint rowst;␊
uint sdam;␊
uint bsma;␊
uint sda10;␊
u_char spd_size;␊
u_char data;␊
u_char cksum;␊
int j;␊
␊
/* Keep the compiler from complaining about potentially uninitialized vars */␊
data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;␊
␊
/*␊
* Read the SDRAM SPD EEPROM via I2C.␊
*/␊
␉i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);␊
␊
i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);␊
spd_size = data;␊
cksum = data;␊
for(j = 1; j < 64; j++) ␊
␉{␉/* read only the checksummed bytes */␊
␉/* note: the I2C address autoincrements when alen == 0 */␊
␉␉i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);␊
␉␉/*printf("addr %d = 0x%02x\n", j, data);*/␊
␉␉if(j == 5) chipselects = data & 0x0F;␊
␉␉else if(j == 6) data_width = data;␊
␉␉else if(j == 7) data_width |= data << 8;␊
␉␉else if(j == 3) rows = data & 0x0F;␊
␉␉else if(j == 4) cols = data & 0x0F;␊
␉␉else if(j == 12) ␊
␉␉{␊
␉␉␉/*␊
␉␉␉␉ * Refresh rate: this assumes the prescaler is set to␊
␉␉␉ * approximately 1uSec per tick.␊
␉␉␉ */␊
␉␉␉switch(data & 0x7F) ␊
␉␉␉{␊
␉␉␉␉␉default:␊
␉␉␉␉␉case 0: psrt = 16; /* 15.625uS */ break;␊
␉␉␉␉␉case 1: psrt = 2; /* 3.9uS */ break;␊
␉␉␉␉␉case 2: psrt = 6; /* 7.8uS */ break;␊
␉␉␉␉␉case 3: psrt = 29; /* 31.3uS */ break;␊
␉␉␉␉␉case 4: psrt = 60; /* 62.5uS */ break;␊
␉␉␉␉␉case 5: psrt = 120; /* 125uS */ break;␊
␉␉␉}␊
␉␉}␊
␉␉else if(j == 17) banks = data;␊
␉␉else if(j == 18) ␊
␉␉{␊
␉␉␉caslatency = 3; /* default CL */␊
#␉␉ if(PESSIMISTIC_SDRAM)␊
␉␉␉␉if((data & 0x04) != 0) caslatency = 3;␊
␉␉␉␉else if((data & 0x02) != 0) caslatency = 2;␊
␉␉␉␉else if((data & 0x01) != 0) caslatency = 1;␊
#␉␉␉else␊
␉␉␉␉if((data & 0x01) != 0) caslatency = 1;␊
␉␉␉␉else if((data & 0x02) != 0) caslatency = 2;␊
␉␉␉␉else if((data & 0x04) != 0) caslatency = 3;␊
#␉␉␉endif␊
␉␉␉else ␊
␉␉␉{␊
␉␉␉printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",␊
␉␉␉␉␉data);␊
␉␉␉}␊
␉␉}␊
␉␉else if(j == 63) ␊
␉␉{␊
␉␉␉if(data != cksum) ␊
␉␉␉{␊
␉␉␉␉printf ("WARNING: Configuration data checksum failure:"␊
␉␉␉␉␉" is 0x%02x, calculated 0x%02x\n",␊
␉␉␉␉data, cksum);␊
␉␉␉}␊
␉␉}␊
␉␉cksum += data;␊
}␊
␊
/* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */␊
if(caslatency < 2) {␊
␉␉printf("CL was %d, forcing to 2\n", caslatency);␊
␉␉caslatency = 2;␊
}␊
if(rows > 14) {␊
␉␉printf("This doesn't look good, rows = %d, should be <= 14\n", rows);␊
␉␉rows = 14;␊
}␊
if(cols > 11) {␊
␉␉printf("This doesn't look good, columns = %d, should be <= 11\n", cols);␊
␉␉cols = 11;␊
}␊
␊
if((data_width != 64) && (data_width != 72))␊
{␊
␉␉printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",␊
␉␉␉data_width);␊
}␊
width = 3;␉␉/* 2^3 = 8 bytes = 64 bits wide */␊
/*␊
* Convert banks into log2(banks)␊
*/␊
if (banks == 2)␉banks = 1;␊
else if(banks == 4)␉banks = 2;␊
else if(banks == 8)␉banks = 3;␊
␊
␊
sdram_size = 1 << (rows + cols + banks + width);␊
␊
#if(CONFIG_PBI == 0)␉/* bank-based interleaving */␊
rowst = ((32 - 6) - (rows + cols + width)) * 2;␊
#else␊
rowst = 32 - (rows + banks + cols + width);␊
#endif␊
␊
or = ~(sdram_size - 1) |␉/* SDAM address mask␉*/␊
␉ ((banks-1) << 13) |␉/* banks per device␉*/␊
␉ (rowst << 9) |␉/* rowst␉␉*/␊
␉ ((rows - 9) << 6);␉/* numr␉␉␉*/␊
␊
␊
/*printf("memctl->memc_or2 = 0x%08x\n", or);*/␊
␊
/*␊
* SDAM specifies the number of columns that are multiplexed␊
* (reference AN2165/D), defined to be (columns - 6) for page␊
* interleave, (columns - 8) for bank interleave.␊
*␊
* BSMA is 14 - max(rows, cols). The bank select lines come␊
* into play above the highest "address" line going into the␊
* the SDRAM.␊
*/␊
#if(CONFIG_PBI == 0)␉/* bank-based interleaving */␊
sdam = cols - 8;␊
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);␊
sda10 = sdam + 2;␊
#else␊
sdam = cols - 6;␊
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);␊
sda10 = sdam;␊
#endif␊
#if(PESSIMISTIC_SDRAM)␊
psdmr = (CONFIG_PBI |\␊
␉ PSDMR_RFEN |\␊
␉ PSDMR_RFRC_16_CLK |\␊
␉ PSDMR_PRETOACT_8W |\␊
␉ PSDMR_ACTTORW_8W |\␊
␉ PSDMR_WRC_4C |\␊
␉ PSDMR_EAMUX |\␊
PSDMR_BUFCMD) |\␊
␉ caslatency |\␊
␉ ((caslatency - 1) << 6) |␉/* LDOTOPRE is CL - 1 */ \␊
␉ (sdam << 24) |\␊
␉ (bsma << 21) |\␊
␉ (sda10 << 18);␊
#else␊
psdmr = (CONFIG_PBI |\␊
␉ PSDMR_RFEN |\␊
␉ PSDMR_RFRC_7_CLK |\␊
␉ PSDMR_PRETOACT_3W |␉/* 1 for 7E parts (fast PC-133) */ \␊
␉ PSDMR_ACTTORW_2W |␉/* 1 for 7E parts (fast PC-133) */ \␊
␉ PSDMR_WRC_1C |␉/* 1 clock + 7nSec */␊
␉ EAMUX |\␊
BUFCMD) |\␊
␉ caslatency |\␊
␉ ((caslatency - 1) << 6) |␉/* LDOTOPRE is CL - 1 */ \␊
␉ (sdam << 24) |\␊
␉ (bsma << 21) |\␊
␉ (sda10 << 18);␊
#endif␊
␉/*printf("psdmr = 0x%08x\n", psdmr);*/␊
␊
/*␊
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):␊
*␊
* "At system reset, initialization software must set up the␊
* programmable parameters in the memory controller banks registers␊
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,␊
* system software should execute the following initialization sequence␊
* for each SDRAM device.␊
*␊
* 1. Issue a PRECHARGE-ALL-BANKS command␊
* 2. Issue eight CBR REFRESH commands␊
* 3. Issue a MODE-SET command to initialize the mode register␊
*␊
* Quote from Micron MT48LC8M16A2 data sheet:␊
*␊
* "...the SDRAM requires a 100uS delay prior to issuing any␊
* command other than a COMMAND INHIBIT or NOP. Starting at some␊
* point during this 100uS period and continuing at least through␊
* the end of this period, COMMAND INHIBIT or NOP commands should␊
* be applied."␊
*␊
* "Once the 100uS delay has been satisfied with at least one COMMAND␊
* INHIBIT or NOP command having been applied, a /PRECHARGE command/␊
* should be applied. All banks must then be precharged, thereby␊
* placing the device in the all banks idle state."␊
*␊
* "Once in the idle state, /two/ AUTO REFRESH cycles must be␊
* performed. After the AUTO REFRESH cycles are complete, the␊
* SDRAM is ready for mode register programming."␊
*␊
* (/emphasis/ mine, gvb)␊
*␊
* The way I interpret this, Micron start up sequence is:␊
* 1. Issue a PRECHARGE-BANK command (initial precharge)␊
* 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")␊
* 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands␊
* 4. Issue a MODE-SET command to initialize the mode register␊
*␊
* --------␊
*␊
* The initial commands are executed by setting P/LSDMR[OP] and␊
* accessing the SDRAM with a single-byte transaction."␊
*␊
* The appropriate BRx/ORx registers have already been set when we␊
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.␊
*/␊
#if 1␊
memctl->memc_mptpr = CFG_MPTPR;␊
memctl->memc_psrt = psrt;␊
␊
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;␊
*ramaddr = c;␊
␊
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;␊
for (i = 0; i < 8; i++)␊
␉*ramaddr = c;␊
␊
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;␊
*ramaddr = c;␊
␊
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;␊
*ramaddr = c;␊
␊
/*␊
* Do it a second time for the second set of chips if the DIMM has␊
* two chip selects (double sided).␊
*/␊
if(chipselects > 1) ␊
␉{␊
ramaddr += sdram_size;␊
␊
␉␉memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;␊
␉␉memctl->memc_or3 = or;␊
␊
␉␉memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;␊
␉␉*ramaddr = c;␊
␊
␉␉memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;␊
␉␉for (i = 0; i < 8; i++)␊
␉␉␉*ramaddr = c;␊
␊
␉␉memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;␊
␉␉*ramaddr = c;␊
␊
␉␉memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;␊
␉␉*ramaddr = c;␊
}␊
#endif␊
␉/*␊
printf("memctl->memc_mptpr = 0x%08x\n", CFG_MPTPR);␊
printf("memctl->memc_psrt = 0x%08x\n", psrt);␊
␊
printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_PREA);␊
printf("ramaddr = 0x%08x\n", ramaddr);␊
␊
printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_CBRR);␊
␊
printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_MRW);␊
␊
printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_NORM | PSDMR_RFEN);␊
␊
immap->im_siu_conf.sc_ppc_acr = 0x00000002;␊
immap->im_siu_conf.sc_ppc_alrh = 0x01267893;␊
immap->im_siu_conf.sc_tescr1 = 0x00004000;␊
␉*/␊
#if 0␊
/* init sdram dimm */␊
ramaddr = (uchar *)CFG_SDRAM_BASE;␊
memctl->memc_psrt = 0x00000010;␊
immap->im_memctl.memc_or2 = 0xFF000CA0;␊
immap->im_memctl.memc_br2 = 0x00000041;␊
memctl->memc_psdmr = 0x296EB452;␊
*ramaddr = c;␊
memctl->memc_psdmr = 0x096EB452;␊
for (i = 0; i < 8; i++)␊
*ramaddr = c;␊
␊
memctl->memc_psdmr = 0x196EB452;␊
*ramaddr = c;␊
memctl->memc_psdmr = 0x416EB452;␊
*ramaddr = c;␊
#endif␉␊
␉/* print info */␊
␉printf("SDRAM configuration read from SPD\n");␊
␉printf("\tSize per side = %dMB\n", sdram_size >> 20);␊
␉printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);␊
␉printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency);␊
␉printf("\tTotal size: ");␊
␊
return (sdram_size * chipselects);␊
␉/*return (16 * 1024 * 1024);*/␊
}␊
board/mpc8266ads/u-boot.lds
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/*␊
* (C) Copyright 2001␊
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
OUTPUT_ARCH(powerpc)␊
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);␊
/* Do we need any of these for elf?␊
__DYNAMIC = 0; */␊
SECTIONS␊
{␊
/* Read-only sections, merged into text segment: */␊
. = + SIZEOF_HEADERS;␊
.interp : { *(.interp) }␊
.hash : { *(.hash)␉␉}␊
.dynsym : { *(.dynsym)␉␉}␊
.dynstr : { *(.dynstr)␉␉}␊
.rel.text : { *(.rel.text)␉␉}␊
.rela.text : { *(.rela.text) ␉}␊
.rel.data : { *(.rel.data)␉␉}␊
.rela.data : { *(.rela.data) ␉}␊
.rel.rodata : { *(.rel.rodata) ␉}␊
.rela.rodata : { *(.rela.rodata) ␉}␊
.rel.got : { *(.rel.got)␉␉}␊
.rela.got : { *(.rela.got)␉␉}␊
.rel.ctors : { *(.rel.ctors)␉}␊
.rela.ctors : { *(.rela.ctors)␉}␊
.rel.dtors : { *(.rel.dtors)␉}␊
.rela.dtors : { *(.rela.dtors)␉}␊
.rel.bss : { *(.rel.bss)␉␉}␊
.rela.bss : { *(.rela.bss)␉␉}␊
.rel.plt : { *(.rel.plt)␉␉}␊
.rela.plt : { *(.rela.plt)␉␉}␊
.init : { *(.init)␉}␊
.plt : { *(.plt) }␊
.text :␊
{␊
cpu/mpc8260/start.o␉(.text)␊
*(.text)␊
*(.fixup)␊
*(.got1)␊
. = ALIGN(16);␊
*(.rodata)␊
*(.rodata1)␊
}␊
.fini : { *(.fini) } =0␊
.ctors : { *(.ctors) }␊
.dtors : { *(.dtors) }␊
␊
/* Read-write section, merged into data segment: */␊
. = (. + 0x0FFF) & 0xFFFFF000;␊
_erotext = .;␊
PROVIDE (erotext = .);␊
.reloc :␊
{␊
*(.got)␊
_GOT2_TABLE_ = .;␊
*(.got2)␊
_FIXUP_TABLE_ = .;␊
*(.fixup)␊
}␊
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;␊
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;␊
␊
.data :␊
{␊
*(.data)␊
*(.data1)␊
*(.sdata)␊
*(.sdata2)␊
*(.dynamic)␊
CONSTRUCTORS␊
}␊
_edata = .;␊
PROVIDE (edata = .);␊
␊
__start___ex_table = .;␊
__ex_table : { *(__ex_table) }␊
__stop___ex_table = .;␊
␊
. = ALIGN(4096);␊
__init_begin = .;␊
.text.init : { *(.text.init) }␊
.data.init : { *(.data.init) }␊
. = ALIGN(4096);␊
__init_end = .;␊
␊
__bss_start = .;␊
.bss :␊
{␊
*(.sbss) *(.scommon)␊
*(.dynbss)␊
*(.bss)␊
*(COMMON)␊
}␊
_end = . ;␊
PROVIDE (end = .);␊
}␊
␊
board/w7o/init.S
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␉ * contents of the SPD EEPROM. If the SPD EEPROM is blank or␊
␉ * erronious, spd_sdram returns 0 in R3.␊
␉ */␊
␉li␉r3,0␊
␉bl␉spd_sdram␊
␉addic.␉r3, r3, 0␉␉/* Check for error, save dram size */␊
␉bne␉..sdri_done␉␉/* If it worked, we're done... */␊
board/walnut405/walnut405.c
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
long int spd_sdram (void);␊
␊
#include <common.h>␊
#include "walnut405.h"␊
#include <asm/processor.h>␊
␊
␊
#include <spd_sdram.h>␊
␊
int board_pre_init (void)␊
{␊
the necessary info for SDRAM controller configuration␊
------------------------------------------------------------------------- */␊
long int initdram (int board_type)␊
{␊
␉long int ret;␊
␊
␉ret = spd_sdram ();␊
␉return ret;␊
{␉␊
␉return spd_sdram (0);␊
}␊
␊
/* ------------------------------------------------------------------------- */␊
cpu/ppc4xx/spd_sdram.c
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*␊
* Based on code by:␊
*␊
* Kenneth Johansson ,Ericsson Business Innovation.␊
* kenneth.johansson@inn.ericsson.se␊
* Kenneth Johansson ,Ericsson AB.␊
* kenneth.johansson@etx.ericsson.se␊
*␊
* hacked up by bill hunter. fixed so we could run before␊
* serial_init and console_init. previous version avoided this by␊
#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )␊
#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )␊
␊
#ifdef CONFIG_W7O␊
#ifdef CONFIG_SPDDRAM_SILENT␊
# define SPD_ERR(x) do { return 0; } while (0)␊
#else␊
# define SPD_ERR(x) do { printf(x); hang(); } while (0)␊
# define SPD_ERR(x) do { printf(x); return(0); } while (0)␊
#endif␊
␊
/*␊
* what we really want is␊
* (1/hertz) but we don't want to use floats so multiply with 10E9␊
*␊
* The error needs to be on the safe side so we want the floor function.␊
* This means we get an exact value or we calculate that our bus frequency is␊
* a bit faster than it really is and thus we don't progam the sdram controller␊
* to run to fast␊
*/␊
#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))␊
␊
/* function prototypes */␊
int spd_read(uint addr);␉␉␉/* prototype */␊
int spd_read(uint addr);␊
␊
␊
/*␊
*␊
* This works on boards that has the same schematics that the IBM walnut has.␊
*␊
* BUG: Don't handle ECC memory␊
* BUG: A few values in the TR register is currently hardcoded␊
* Input: null for default I2C spd functions or a pointer to a custom function␊
* returning spd_data.␊
*/␊
␊
long int spd_sdram(void)␊
long int spd_sdram(int(read_spd)(uint addr))␊
{␊
␉int bus_period,tmp,row,col;␊
␉int total_size,bank_size,bank_code;␊
␉int ecc_on;␊
␉int mode = 4;␊
␉int bank_cnt = 1;␊
␉int mode;␊
␉int bank_cnt;␊
␊
␉int sdram0_pmit=0x07c00000;␊
␉int sdram0_besr0=-1;␊
␊
␉int t_rp;␊
␉int t_rcd;␊
␉int t_rc = 70; /* This value not available in SPD_EEPROM */␊
␉int min_cas = 2;␊
␉int t_ras;␊
␉int t_rc;␊
␉int min_cas;␊
␊
␉if(read_spd == 0){␊
␉␉read_spd=spd_read;␊
␉/*␊
␉ * Make sure I2C controller is initialized␊
␉ * before continuing.␊
␉ */␊
␉i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);␊
␉␉i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);␊
␉}␊
␊
␊
␉/*␊
␉ * Calculate the bus period, we do it this␊
␉bus_period = sdram_HZ_to_ns(tmp);␉/* get sdram speed */␊
␊
␉/* Make shure we are using SDRAM */␊
␉if (spd_read(2) != 0x04){␊
␉if (read_spd(2) != 0x04){␊
SPD_ERR("SDRAM - non SDRAM memory module found\n");␊
␉ }␊
␊
* use the min supported mode␊
*/␊
␊
␉tmp = spd_read(127) & 0x6;␊
␉tmp = read_spd(127) & 0x6;␊
if(tmp == 0x02){ ␉ /* only cas = 2 supported */␊
␉ min_cas = 2;␊
/* ␉ t_ck = spd_read(9); */␊
/* ␉ t_ac = spd_read(10); */␊
/* ␉ t_ck = read_spd(9); */␊
/* ␉ t_ac = read_spd(10); */␊
␉ }␊
else if (tmp == 0x04){ /* only cas = 3 supported */␊
␉ min_cas = 3;␊
/* ␉ t_ck = spd_read(9); */␊
/* ␉ t_ac = spd_read(10); */␊
/* ␉ t_ck = read_spd(9); */␊
/* ␉ t_ac = read_spd(10); */␊
␉ }␊
else if (tmp == 0x06){ /* 2,3 supported, so use 2 */␊
␉ min_cas = 2;␊
/* ␉ t_ck = spd_read(23); */␊
/* ␉ t_ac = spd_read(24); */␊
/* ␉ t_ck = read_spd(23); */␊
/* ␉ t_ac = read_spd(24); */␊
␉ }␊
else {␊
␉ SPD_ERR("SDRAM - unsupported CAS latency \n");␊
␉}␊
␊
/* get some timing values, t_rp,t_rcd␊
/* get some timing values, t_rp,t_rcd,t_ras,t_rc␊
*/␊
t_rp = spd_read(27);␊
t_rcd = spd_read(29);␊
␊
t_rp = read_spd(27);␊
t_rcd = read_spd(29);␊
t_ras = read_spd(30);␊
t_rc = t_ras + t_rp;␊
␊
/* The following timing calcs subtract 1 before deviding.␊
* this has effect of using ceiling intead of floor rounding,␊
* this has effect of using ceiling instead of floor rounding,␊
* and also subtracting 1 to convert number to reg value␊
*/␊
/* set up CASL */␊
sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;␊
/* set up CTP */␊
tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;␊
if(tmp<1) SPD_ERR("SDRAM - unsupported prech to act time (Trp)\n");␊
if(tmp<1) tmp=1;␊
sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;␊
/* set LDF␉= 2 cycles, reg value = 1 */␊
sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;␊
/* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */␊
␉tmp = ((t_rc - 1) / bus_period)-4;␊
␉tmp = ( (t_rc - 1) / bus_period)-3;␊
␉if(tmp<0)tmp=0;␊
␉if(tmp>6)tmp=6;␊
␉sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;␊
/*------------------------------------------------------------------␊
configure RTR register␊
-------------------------------------------------------------------*/␊
row = spd_read(3);␊
col = spd_read(4);␊
tmp = spd_read(12) & 0x7f ; /* refresh type less self refresh bit */␊
row = read_spd(3);␊
col = read_spd(4);␊
tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */␊
switch(tmp){␊
␉case 0x00:␊
␉ tmp=15625;␊
determine the number of banks used␊
-------------------------------------------------------------------*/␊
␉/* byte 7:6 is module data width */␊
␉if(spd_read(7) != 0)␊
␉if(read_spd(7) != 0)␊
␉ SPD_ERR("SDRAM - unsupported module width\n");␊
␉tmp = spd_read(6);␊