GTA04 U-Boot

GTA04 U-Boot Commit Details

Date:2005-04-05 18:26:47 (8 years 1 month ago)
Author:wdenk
Branch:gta04
Commit:f5c5ef4a1fa7dcf90fd74f795a131d07377406ab
Parents: 3dd7f0f0ca1720aee5d8b1b40fd2ae093deb81a0
Message:Add support for TQM8560 board
Changes:
Cboard/tqm8540/Makefile → board/tqm8560/Makefile
Cboard/tqm8540/config.mk → board/tqm8560/config.mk
Cboard/tqm8540/init.S → board/tqm8560/init.S
Cboard/mpc8560ads/mpc8560ads.c → board/tqm8560/tqm8560.c
Cboard/tqm8540/u-boot.lds → board/tqm8560/u-boot.lds
Cinclude/configs/TQM8540.h → include/configs/TQM8560.h
MCHANGELOG (1 diff)
MMakefile (1 diff)
Minclude/configs/TQM8540.h (5 diffs)

File differences

CHANGELOG
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Changes for U-Boot 1.1.3:␊
======================================================================␊
␊
* Add support for TQM8560 board␊
␊
* Add FEC support for TQM8540 board.␊
Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC␊
␊
Makefile
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TQM8540_config: unconfig␊
␉@./mkconfig $(@:_config=) ppc mpc85xx tqm8540␊
␊
TQM8560_config: unconfig␊
␉@./mkconfig $(@:_config=) ppc mpc85xx tqm8560␊
␊
#########################################################################␊
## 74xx/7xx Systems␊
#########################################################################␊
board/tqm8560/Makefile
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#␊
# (C) Copyright 2001␊
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.␊
#␊
# See file CREDITS for list of people who contributed to this␊
# project.␊
#␊
# This program is free software; you can redistribute it and/or␊
# modify it under the terms of the GNU General Public License as␊
# published by the Free Software Foundation; either version 2 of␊
# the License, or (at your option) any later version.␊
#␊
# This program is distributed in the hope that it will be useful,␊
# but WITHOUT ANY WARRANTY; without even the implied warranty of␊
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.␉See the␊
# GNU General Public License for more details.␊
#␊
# You should have received a copy of the GNU General Public License␊
# along with this program; if not, write to the Free Software␊
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
# MA 02111-1307 USA␊
#␊
␊
include $(TOPDIR)/config.mk␊
␊
LIB␉= lib$(BOARD).a␊
␊
OBJS␉:= $(BOARD).o␊
SOBJS␉:= init.o␊
#SOBJS␉:=␊
␊
$(LIB): $(OBJS) $(SOBJS)␊
␉$(AR) crv $@ $(OBJS)␊
␊
clean:␊
␉rm -f $(OBJS) $(SOBJS)␊
␊
distclean:␉clean␊
␉rm -f $(LIB) core *.bak .depend␊
␊
#########################################################################␊
␊
.depend:␉Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)␊
␉␉$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@␊
␊
-include .depend␊
␊
#########################################################################␊
board/tqm8560/config.mk
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# Copyright 2004 Freescale Semiconductor.␊
# Modified by Xianghua Xiao, X.Xiao@motorola.com␊
# (C) Copyright 2002,Motorola Inc.␊
#␊
# See file CREDITS for list of people who contributed to this␊
# project.␊
#␊
# This program is free software; you can redistribute it and/or␊
# modify it under the terms of the GNU General Public License as␊
# published by the Free Software Foundation; either version 2 of␊
# the License, or (at your option) any later version.␊
#␊
# This program is distributed in the hope that it will be useful,␊
# but WITHOUT ANY WARRANTY; without even the implied warranty of␊
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
# GNU General Public License for more details.␊
#␊
# You should have received a copy of the GNU General Public License␊
# along with this program; if not, write to the Free Software␊
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
# MA 02111-1307 USA␊
#␊
␊
#␊
# tqm8560 board␊
# default CCARBAR is at 0xff700000␊
# assume U-Boot is less than 256k␊
#␊
TEXT_BASE = 0xfffc0000␊
board/tqm8560/init.S
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/*␊
* Copyright 2004 Freescale Semiconductor.␊
* Copyright (C) 2002,2003, Motorola Inc.␊
* Xianghua Xiao <X.Xiao@motorola.com>␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.␉ See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
#include <ppc_asm.tmpl>␊
#include <ppc_defs.h>␊
#include <asm/cache.h>␊
#include <asm/mmu.h>␊
#include <config.h>␊
#include <mpc85xx.h>␊
␊
␊
/*␊
* TLB0 and TLB1 Entries␊
*␊
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.␊
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after␊
* these TLB entries are established.␊
*␊
* The TLB entries for DDR are dynamically setup in spd_sdram()␊
* and use TLB1 Entries 8 through 15 as needed according to the␊
* size of DDR memory.␊
*␊
* MAS0: tlbsel, esel, nv␊
* MAS1: valid, iprot, tid, ts, tsize␊
* MAS2: epn, sharen, x0, x1, w, i, m, g, e␊
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr␊
*/␊
␊
#define entry_start \␊
␉mflr␉r1␉;␉\␊
␉bl␉0f␉;␊
␊
#define entry_end \␊
0:␉mflr␉r0␉;␉\␊
␉mtlr␉r1␉;␉\␊
␉blr␉␉;␊
␊
␊
␉.section␉.bootpg, "ax"␊
␉.globl␉tlb1_entry␊
tlb1_entry:␊
␉entry_start␊
␊
␉/*␊
␉ * Number of TLB0 and TLB1 entries in the following table␊
␉ */␊
␉.long 13␊
␊
␉/*␊
␉ * TLB0␉␉16K␉Cacheable, non-guarded␊
␉ * 0xd001_0000␉16K␉Temporary Global data for initialization␊
␉ *␊
␉ * Use four 4K TLB0 entries. These entries must be cacheable␊
␉ * as they provide the bootstrap memory before the memory␊
␉ * controler and real memory have been configured.␊
␉ *␊
␉ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,␊
␉ * and must not collide with other TLB0 entries.␊
␉ */␊
␉.long TLB1_MAS0(0, 0, 0)␊
␉.long TLB1_MAS1(1, 0, 0, 0, 0)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),␊
␉␉␉0,0,0,0,0,0,0,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),␊
␉␉␉0,0,0,0,0,1,0,1,0,1)␊
␊
␉.long TLB1_MAS0(0, 0, 0)␊
␉.long TLB1_MAS1(1, 0, 0, 0, 0)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),␊
␉␉␉0,0,0,0,0,0,0,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),␊
␉␉␉0,0,0,0,0,1,0,1,0,1)␊
␊
␉.long TLB1_MAS0(0, 0, 0)␊
␉.long TLB1_MAS1(1, 0, 0, 0, 0)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),␊
␉␉␉0,0,0,0,0,0,0,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),␊
␉␉␉0,0,0,0,0,1,0,1,0,1)␊
␊
␉.long TLB1_MAS0(0, 0, 0)␊
␉.long TLB1_MAS1(1, 0, 0, 0, 0)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),␊
␉␉␉0,0,0,0,0,0,0,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),␊
␉␉␉0,0,0,0,0,1,0,1,0,1)␊
␊
␊
␉/*␊
␉ * TLB 0, 1:␉32M␉Non-cacheable, guarded␊
␉ * 0xfe000000␉32M␉FLASH␊
␉ * Out of reset this entry is only 4K.␊
␉ */␊
␉.long TLB1_MAS0(1, 1, 0)␊
␉.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)␊
␉.long TLB1_MAS0(1, 0, 0)␊
␉.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)␊
␊
␉/*␊
␉ * TLB 2:␉256M␉Non-cacheable, guarded␊
␉ * 0x80000000␉256M␉PCI1 MEM First half␊
␉ */␊
␉.long TLB1_MAS0(1, 2, 0)␊
␉.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)␊
␊
␉/*␊
␉ * TLB 3:␉256M␉Non-cacheable, guarded␊
␉ * 0x90000000␉256M␉PCI1 MEM Second half␊
␉ */␊
␉.long TLB1_MAS0(1, 3, 0)␊
␉.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),␊
␉␉␉0,0,0,0,1,0,1,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),␊
␉␉␉0,0,0,0,0,1,0,1,0,1)␊
␊
␉/*␊
␉ * TLB 4:␉256M␉Non-cacheable, guarded␊
␉ * 0xc0000000␉256M␉Rapid IO MEM First half␊
␉ */␊
␉.long TLB1_MAS0(1, 4, 0)␊
␉.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)␊
␊
␉/*␊
␉ * TLB 5:␉256M␉Non-cacheable, guarded␊
␉ * 0xd0000000␉256M␉Rapid IO MEM Second half␊
␉ */␊
␉.long TLB1_MAS0(1, 5, 0)␊
␉.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),␊
␉␉␉0,0,0,0,1,0,1,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),␊
␉␉␉0,0,0,0,0,1,0,1,0,1)␊
␊
␉/*␊
␉ * TLB 6:␉64M␉Non-cacheable, guarded␊
␉ * 0xe000_0000␉1M␉CCSRBAR␊
␉ * 0xe200_0000␉16M␉PCI1 IO␊
␉ */␊
␉.long TLB1_MAS0(1, 6, 0)␊
␉.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)␊
␊
#if !defined(CONFIG_SPD_EEPROM)␊
␉/*␊
␉ * TLB 7:␉256M␉DDR␊
␉ * 0x00000000 256M␉DDR System memory␊
␉ * Without SPD EEPROM configured DDR, this must be setup manually.␊
␉ * Make sure the TLB count at the top of this table is correct.␊
␉ * Likely it needs to be increased by two for these entries.␊
␉ */␊
␉.long TLB1_MAS0(1, 7, 0)␊
␉.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)␊
␉.long TLB1_MAS0(1, 8, 0)␊
␉.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)␊
␉.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)␊
␉.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)␊
#endif␊
␊
␉entry_end␊
␊
/*␊
* LAW(Local Access Window) configuration:␊
*␊
* 0x0000_0000␉ 0x7fff_ffff␉ DDR␉␉␉ 2G␊
* 0x8000_0000␉ 0x9fff_ffff␉ PCI1 MEM␉␉ 512M␊
* 0xc000_0000␉ 0xdfff_ffff␉ RapidIO␉␉ 512M␊
* 0xe000_0000␉ 0xe000_ffff␉ CCSR␉␉␉ 1M␊
* 0xe200_0000␉ 0xe2ff_ffff␉ PCI1 IO␉␉ 16M␊
* 0xf800_0000␉ 0xf80f_ffff␉ BCSR␉␉␉ 1M␊
* 0xfe00_0000␉ 0xffff_ffff␉ FLASH (boot bank)␉ 32M␊
*␊
* Notes:␊
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.␊
* If flash is 8M at default position (last 8M), no LAW needed.␊
*/␊
␊
#if !defined(CONFIG_SPD_EEPROM)␊
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)␊
#define LAWAR0␉(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))␊
#else␊
#define LAWBAR0 0␊
#define LAWAR0␉((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)␊
#endif␊
␊
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)␊
#define LAWAR1␉(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))␊
␊
#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)␊
#define LAWAR2␉(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))␊
␊
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)␊
#define LAWAR3␉(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))␊
␊
/*␊
* Rapid IO at 0xc000_0000 for 512 M␊
*/␊
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)␊
#define LAWAR4␉(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))␊
␊
␊
␉.section .bootpg, "ax"␊
␉.globl␉law_entry␊
law_entry:␊
␉entry_start␊
␉.long 0x05␊
␉.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3␊
␉.long LAWBAR4,LAWAR4␊
␉entry_end␊
board/tqm8560/tqm8560.c
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/*␊
* Copyright 2005 DENX Software Engineering␊
* Copyright 2004 Freescale Semiconductor.␊
* (C) Copyright 2002,2003, Motorola Inc.␊
* Xianghua Xiao, (X.Xiao@motorola.com)␊
*␊
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
␊
#include <common.h>␊
#include <pci.h>␊
#include <asm/processor.h>␊
#include <asm/immap_85xx.h>␊
#include <ioports.h>␊
#include <spd.h>␊
␊
#if defined(CONFIG_DDR_ECC)␊
extern void ddr_enable_ecc (unsigned int dram_size);␊
#endif␊
␊
extern long int spd_sdram (void);␊
␊
void local_bus_init (void);␊
long int fixed_sdram (void);␊
␊
/*␊
* I/O Port configuration table␊
*␊
* if conf is 1, then that port pin will be configured at boot time␊
* according to the five values podr/pdir/ppar/psor/pdat for that entry␊
*/␊
␊
const iop_conf_t iop_conf_tab[4][32] = {␊
␊
/* Port A configuration */␊
{ /* conf ppar psor pdir podr pdat */␊
␉/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */␊
␉/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */␊
␉/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */␊
␉/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */␊
␉/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */␊
␉/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */␊
␉/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */␊
␉/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */␊
␉/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */␊
␉/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */␊
␉/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */␊
␉/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */␊
␉/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */␊
␉/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */␊
␉/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */␊
␉/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */␊
␉/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */␊
␉/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */␊
␉/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */␊
␉/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */␊
␉/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */␊
␉/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */␊
␉/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */␊
␉/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */␊
␉/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */␊
␉/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */␊
␉/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */␊
␉/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */␊
␉/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */␊
␉/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */␊
␉/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */␊
␉/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */␊
},␊
␊
/* Port B configuration */␊
{ /* conf ppar psor pdir podr pdat */␊
␉/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */␊
␉/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */␊
␉/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */␊
␉/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */␊
␉/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */␊
␉/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */␊
␉/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */␊
␉/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */␊
␉/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */␊
␉/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */␊
␉/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */␊
␉/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */␊
␉/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */␊
␉/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */␊
␉/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */␊
␉/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */␊
␉/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */␊
␉/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */␊
␉/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */␊
␉/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */␊
␉/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */␊
␉/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */␊
␉/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */␊
␉/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */␊
␉/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */␊
␉/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */␊
␉/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */␊
␉/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */␊
␉/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */␊
},␊
␊
/* Port C */␊
{ /* conf ppar psor pdir podr pdat */␊
␉/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */␊
␉/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */␊
␉/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */␊
␉/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */␊
␉/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */␊
␉/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */␊
␉/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */␊
␉/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */␊
␉/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */␊
␉/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */␊
␉/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */␊
␉/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */␊
␉/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */␊
␉/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */␊
␉/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */␊
␉/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */␊
␉/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */␊
␉/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */␊
␉/* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */␊
␉/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */␊
␉/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */␊
␉/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */␊
␉/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */␊
␉/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */␊
␉/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */␊
␉/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */␊
␉/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */␊
␉/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */␊
␉/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */␊
␉/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */␊
␉/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */␊
␉/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */␊
},␊
␊
/* Port D */␊
{ /* conf ppar psor pdir podr pdat */␊
␉/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */␊
␉/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */␊
␉/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */␊
␉/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */␊
␉/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */␊
␉/* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */␊
␉/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */␊
␉/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */␊
␉/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */␊
␉/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */␊
␉/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */␊
␉/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */␊
␉/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */␊
␉/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */␊
␉/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */␊
␉/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */␊
␉/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */␊
␉/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */␊
␉/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */␊
␉/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */␊
␉/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */␊
␉/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */␊
␉/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */␊
␉/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */␊
␉/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */␊
␉/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */␊
␉/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */␊
␉/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */␊
␉/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */␊
␉/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */␊
}␊
};␊
␊
␊
int board_early_init_f (void)␊
{␊
␉return 0;␊
}␊
␊
int checkboard (void)␊
{␊
␉puts ("Board: TQM8560\n");␊
␊
#ifdef CONFIG_PCI␊
␉printf ("PCI1: 32 bit, %d MHz (compiled)\n",␊
␉␉CONFIG_SYS_CLK_FREQ / 1000000);␊
#else␊
␉printf ("PCI1: disabled\n");␊
#endif␊
␉/*␊
␉ * Initialize local bus.␊
␉ */␊
␉local_bus_init ();␊
␊
␉return 0;␊
}␊
␊
␊
long int initdram (int board_type)␊
{␊
␉long dram_size = 0;␊
␉extern long spd_sdram (void);␊
␉volatile immap_t *immap = (immap_t *) CFG_IMMR;␊
␊
#if defined(CONFIG_DDR_DLL)␊
␉{␊
␉␉volatile ccsr_gur_t *gur = &immap->im_gur;␊
␉␉uint temp_ddrdll = 0;␊
␊
␉␉/*␊
␉␉ * Work around to stabilize DDR DLL␊
␉␉ */␊
␉␉temp_ddrdll = gur->ddrdllcr;␊
␉␉gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;␊
␉␉asm ("sync;isync;msync");␊
␉}␊
#endif␊
␊
#if defined(CONFIG_SPD_EEPROM)␊
␉dram_size = spd_sdram ();␊
#else␊
␉dram_size = fixed_sdram ();␊
#endif␊
␊
#if defined(CONFIG_DDR_ECC)␊
␉/*␊
␉ * Initialize and enable DDR ECC.␊
␉ */␊
␉ddr_enable_ecc (dram_size);␊
#endif␊
␊
␉return dram_size;␊
}␊
␊
␊
/*␊
* Initialize Local Bus␊
*/␊
␊
void local_bus_init (void)␊
{␊
␉volatile immap_t *immap = (immap_t *) CFG_IMMR;␊
␉volatile ccsr_gur_t *gur = &immap->im_gur;␊
␉volatile ccsr_lbc_t *lbc = &immap->im_lbc;␊
␊
␉uint clkdiv;␊
␉uint lbc_hz;␊
␉sys_info_t sysinfo;␊
␊
␉/*␊
␉ * Errata LBC11.␊
␉ * Fix Local Bus clock glitch when DLL is enabled.␊
␉ *␊
␉ * If localbus freq is < 66Mhz, DLL bypass mode must be used.␊
␉ * If localbus freq is > 133Mhz, DLL can be safely enabled.␊
␉ * Between 66 and 133, the DLL is enabled with an override workaround.␊
␉ */␊
␊
␉get_sys_info (&sysinfo);␊
␉clkdiv = lbc->lcrr & 0x0f;␊
␉lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;␊
␊
␉if (lbc_hz < 66) {␊
␉␉lbc->lcrr = CFG_LBC_LCRR | 0x80000000;␉/* DLL Bypass */␊
␉␉lbc->ltedr = 0xa4c80000;␉/* DK: !!! */␊
␊
␉} else if (lbc_hz >= 133) {␊
␉␉lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);␉/* DLL Enabled */␊
␊
␉} else {␊
␉␉/*␊
␉␉ * On REV1 boards, need to change CLKDIV before enable DLL.␊
␉␉ * Default CLKDIV is 8, change it to 4 temporarily.␊
␉␉ */␊
␉␉uint pvr = get_pvr ();␊
␉␉uint temp_lbcdll = 0;␊
␊
␉␉if (pvr == PVR_85xx_REV1) {␊
␉␉␉/* FIXME: Justify the high bit here. */␊
␉␉␉lbc->lcrr = 0x10000004;␊
␉␉}␊
␊
␉␉lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);␉/* DLL Enabled */␊
␉␉udelay (200);␊
␊
␉␉/*␊
␉␉ * Sample LBC DLL ctrl reg, upshift it to set the␊
␉␉ * override bits.␊
␉␉ */␊
␉␉temp_lbcdll = gur->lbcdllcr;␊
␉␉gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);␊
␉␉asm ("sync;isync;msync");␊
␉}␊
}␊
␊
␊
#if defined(CFG_DRAM_TEST)␊
int testdram (void)␊
{␊
␉uint *pstart = (uint *) CFG_MEMTEST_START;␊
␉uint *pend = (uint *) CFG_MEMTEST_END;␊
␉uint *p;␊
␊
␉printf ("SDRAM test phase 1:\n");␊
␉for (p = pstart; p < pend; p++)␊
␉␉*p = 0xaaaaaaaa;␊
␊
␉for (p = pstart; p < pend; p++) {␊
␉␉if (*p != 0xaaaaaaaa) {␊
␉␉␉printf ("SDRAM test fails at: %08x\n", (uint) p);␊
␉␉␉return 1;␊
␉␉}␊
␉}␊
␊
␉printf ("SDRAM test phase 2:\n");␊
␉for (p = pstart; p < pend; p++)␊
␉␉*p = 0x55555555;␊
␊
␉for (p = pstart; p < pend; p++) {␊
␉␉if (*p != 0x55555555) {␊
␉␉␉printf ("SDRAM test fails at: %08x\n", (uint) p);␊
␉␉␉return 1;␊
␉␉}␊
␉}␊
␊
␉printf ("SDRAM test passed.\n");␊
␉return 0;␊
}␊
#endif␊
␊
␊
#if !defined(CONFIG_SPD_EEPROM)␊
/*************************************************************************␊
* fixed sdram init -- doesn't use serial presence detect.␊
************************************************************************/␊
long int fixed_sdram (void)␊
{␊
#ifndef CFG_RAMBOOT␊
␉volatile immap_t *immap = (immap_t *) CFG_IMMR;␊
␉volatile ccsr_ddr_t *ddr = &immap->im_ddr;␊
␊
␉ddr->cs0_bnds = CFG_DDR_CS0_BNDS;␊
␉ddr->cs0_config = CFG_DDR_CS0_CONFIG;␊
␉ddr->timing_cfg_1 = CFG_DDR_TIMING_1;␊
␉ddr->timing_cfg_2 = CFG_DDR_TIMING_2;␊
␉ddr->sdram_mode = CFG_DDR_MODE;␊
␉ddr->sdram_interval = CFG_DDR_INTERVAL;␊
␉ddr->err_disable = 0x0000000D;␊
#if defined (CONFIG_DDR_ECC)␊
␉ddr->err_disable = 0x0000000D;␊
␉ddr->err_sbe = 0x00ff0000;␊
#endif␊
␉asm ("sync;isync;msync");␊
␉udelay (500);␊
#if defined (CONFIG_DDR_ECC)␊
␉/* Enable ECC checking */␊
␉ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);␊
#else␊
␉ddr->sdram_cfg = CFG_DDR_CONTROL;␊
#endif␊
␉asm ("sync; isync; msync");␊
␉udelay (500);␊
#endif␊
␉return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);␊
}␊
#endif /* !defined(CONFIG_SPD_EEPROM) */␊
␊
␊
#if defined(CONFIG_PCI)␊
/*␊
* Initialize PCI Devices, report devices found.␊
*/␊
␊
#ifndef CONFIG_PCI_PNP␊
static struct pci_config_table pci_mpc85xxads_config_table[] = {␊
␉{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,␊
␉ PCI_IDSEL_NUMBER, PCI_ANY_ID,␊
␉ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,␊
␉␉␉␉ PCI_ENET0_MEMADDR,␊
␉␉␉␉ PCI_COMMAND_MEMORY |␊
␉␉␉␉ PCI_COMMAND_MASTER}},␊
␉{}␊
};␊
#endif␊
␊
␊
static struct pci_controller hose = {␊
#ifndef CONFIG_PCI_PNP␊
␉config_table:pci_mpc85xxads_config_table,␊
#endif␊
};␊
␊
#endif /* CONFIG_PCI */␊
␊
␊
void pci_init_board (void)␊
{␊
#ifdef CONFIG_PCI␊
␉extern void pci_mpc85xx_init (struct pci_controller *hose);␊
␊
␉pci_mpc85xx_init (&hose);␊
#endif /* CONFIG_PCI */␊
}␊
board/tqm8560/u-boot.lds
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/*␊
* (C) Copyright 2002,2003, Motorola,Inc.␊
* Xianghua Xiao, X.Xiao@motorola.com.␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.␉ See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
OUTPUT_ARCH(powerpc)␊
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);␊
/* Do we need any of these for elf?␊
__DYNAMIC = 0; */␊
SECTIONS␊
{␊
.resetvec 0xFFFFFFFC :␊
{␊
*(.resetvec)␊
} = 0xffff␊
␊
.bootpg 0xFFFFF000 :␊
{␊
cpu/mpc85xx/start.o (.bootpg)␊
board/tqm8560/init.o (.bootpg)␊
} = 0xffff␊
␊
/* Read-only sections, merged into text segment: */␊
. = + SIZEOF_HEADERS;␊
.interp : { *(.interp) }␊
.hash␉␉ : { *(.hash)␉␉}␊
.dynsym␉ : { *(.dynsym)␉␉}␊
.dynstr␉ : { *(.dynstr)␉␉}␊
.rel.text␉ : { *(.rel.text)␉␉}␊
.rela.text␉ : { *(.rela.text)␉}␊
.rel.data␉ : { *(.rel.data)␉␉}␊
.rela.data␉ : { *(.rela.data)␉}␊
.rel.rodata␉ : { *(.rel.rodata)␉}␊
.rela.rodata␉ : { *(.rela.rodata)␉}␊
.rel.got␉ : { *(.rel.got)␉␉}␊
.rela.got␉ : { *(.rela.got)␉␉}␊
.rel.ctors␉ : { *(.rel.ctors)␉}␊
.rela.ctors␉ : { *(.rela.ctors)␉}␊
.rel.dtors␉ : { *(.rel.dtors)␉}␊
.rela.dtors␉ : { *(.rela.dtors)␉}␊
.rel.bss␉ : { *(.rel.bss)␉␉}␊
.rela.bss␉ : { *(.rela.bss)␉␉}␊
.rel.plt␉ : { *(.rel.plt)␉␉}␊
.rela.plt␉ : { *(.rela.plt)␉␉}␊
.init␉␉ : { *(.init)␉}␊
.plt : { *(.plt) }␊
.text␉ :␊
{␊
cpu/mpc85xx/start.o (.text)␊
board/tqm8560/init.o (.text)␊
cpu/mpc85xx/traps.o (.text)␊
cpu/mpc85xx/interrupts.o (.text)␊
cpu/mpc85xx/cpu_init.o (.text)␊
cpu/mpc85xx/cpu.o (.text)␊
cpu/mpc85xx/tsec.o (.text)␊
cpu/mpc85xx/speed.o (.text)␊
cpu/mpc85xx/pci.o (.text)␊
common/dlmalloc.o (.text)␊
lib_generic/crc32.o (.text)␊
lib_ppc/extable.o (.text)␊
lib_generic/zlib.o (.text)␊
*(.text)␊
*(.fixup)␊
*(.got1)␊
}␊
_etext = .;␊
PROVIDE (etext = .);␊
.rodata :␊
{␊
*(.rodata)␊
*(.rodata1)␊
*(.rodata.str1.4)␊
}␊
.fini␉ : { *(.fini) } =0␊
.ctors : { *(.ctors) }␊
.dtors : { *(.dtors) }␊
␊
/* Read-write section, merged into data segment: */␊
. = (. + 0x00FF) & 0xFFFFFF00;␊
_erotext = .;␊
PROVIDE (erotext = .);␊
.reloc :␊
{␊
*(.got)␊
_GOT2_TABLE_ = .;␊
*(.got2)␊
_FIXUP_TABLE_ = .;␊
*(.fixup)␊
}␊
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;␊
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;␊
␊
.data␉ :␊
{␊
*(.data)␊
*(.data1)␊
*(.sdata)␊
*(.sdata2)␊
*(.dynamic)␊
CONSTRUCTORS␊
}␊
_edata = .;␊
PROVIDE (edata = .);␊
␊
__u_boot_cmd_start = .;␊
.u_boot_cmd : { *(.u_boot_cmd) }␊
__u_boot_cmd_end = .;␊
␊
__start___ex_table = .;␊
__ex_table : { *(__ex_table) }␊
__stop___ex_table = .;␊
␊
. = ALIGN(256);␊
__init_begin = .;␊
.text.init : { *(.text.init) }␊
.data.init : { *(.data.init) }␊
. = ALIGN(256);␊
__init_end = .;␊
␊
__bss_start = .;␊
.bss␉ :␊
{␊
*(.sbss) *(.scommon)␊
*(.dynbss)␊
*(.bss)␊
*(COMMON)␊
}␊
_end = . ;␊
PROVIDE (end = .);␊
}␊
include/configs/TQM8540.h
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#define CONFIG_DDR_DLL␉␉␉/* possible DLL fix needed */␊
#define CONFIG_DDR_2T_TIMING␉␉/* Sets the 2T timing bit */␊
␊
␊
/*␊
* sysclk for MPC85xx␊
*␊
#define CONFIG_SYS_CLK_FREQ␉33000000␊
#endif␊
␊
␊
/*␊
* These can be toggled for performance analysis, otherwise use default.␊
*/␊
#define CFG_MEMTEST_START␉0x00000000␉/* memtest region */␊
#define CFG_MEMTEST_END␉␉0x10000000␊
␊
␊
/*␊
* Base addresses -- Note these are effective addresses where the␊
* actual resources get mapped (not physical addresses)␊
*/␊
#define CFG_CCSRBAR_DEFAULT␉0xFF700000␉/* CCSRBAR Default */␊
#define CFG_CCSRBAR␉␉0xe0000000␉/* relocated CCSRBAR */␊
#define CFG_CCSRBAR␉␉0xE0000000␉/* relocated CCSRBAR */␊
#define CFG_IMMR␉␉CFG_CCSRBAR␉/* PQII uses CFG_IMMR */␊
␊
␊
/*␊
* DDR Setup␊
*/␊
#define CFG_DDR_INTERVAL␉0x05160100␉/* autocharge,no open page */␊
#endif␊
␊
␊
/*␊
* Flash on the Local Bus␊
*/␊
␊
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV␉| \␊
␉␉␉␉ADD_PCI_CMD␉| \␊
␉␉␉␉CFG_CMD_PING␉| \␊
␉␉␉␉CFG_CMD_I2C␉)␊
␉␉␉␉CFG_CMD_I2C␉| \␊
␉␉␉␉CFG_CMD_PING␉)␊
#include <cmd_confdefs.h>␊
␊
#undef CONFIG_WATCHDOG␉␉␉/* watchdog disabled */␊
include/configs/TQM8560.h
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/*␊
* Copyright 2005 DENX Software Engineering␊
* Wolfgang Denk <wd@denx.de>␊
* Copyright 2004 Freescale Semiconductor.␊
* (C) Copyright 2002,2003 Motorola,Inc.␊
* Xianghua Xiao <X.Xiao@motorola.com>␊
*␊
* See file CREDITS for list of people who contributed to this␊
* project.␊
*␊
* This program is free software; you can redistribute it and/or␊
* modify it under the terms of the GNU General Public License as␊
* published by the Free Software Foundation; either version 2 of␊
* the License, or (at your option) any later version.␊
*␊
* This program is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.␉ See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with this program; if not, write to the Free Software␊
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,␊
* MA 02111-1307 USA␊
*/␊
␊
/*␊
* TQM8560 board configuration file␊
*␊
* Make sure you change the MAC address and other network params first,␊
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.␊
*/␊
␊
#ifndef __CONFIG_H␊
#define __CONFIG_H␊
␊
/* High Level Configuration Options */␊
#define CONFIG_BOOKE␉␉1␉/* BOOKE */␊
#define CONFIG_E500␉␉1␉/* BOOKE e500 family */␊
#define CONFIG_MPC85xx␉␉1␉/* MPC8540/MPC8560 */␊
#define CONFIG_MPC8560␉␉1␉/* MPC8560 specific */␊
#define CONFIG_TQM8560␉␉1␉/* TQM8560 board specific */␊
␊
#undef CONFIG_PCI␊
#define CONFIG_TSEC_ENET␉␉/* tsec ethernet support */␊
#undef CONFIG_DDR_ECC␉␉␉/* only for ECC DDR module */␊
#define CONFIG_DDR_DLL␉␉␉/* possible DLL fix needed */␊
#define CONFIG_DDR_2T_TIMING␉␉/* Sets the 2T timing bit */␊
␊
/*␊
* sysclk for MPC85xx␊
*␊
* Two valid values are:␊
* 33000000␊
* 66000000␊
*␊
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz␊
* is likely the desired value here, so that is now the default.␊
* The board, however, can run at 66MHz. In any event, this value␊
* must match the settings of some switches. Details can be found␊
* in the README.mpc85xxads.␊
*/␊
␊
#ifndef CONFIG_SYS_CLK_FREQ␊
#define CONFIG_SYS_CLK_FREQ␉33000000␊
#endif␊
␊
/*␊
* These can be toggled for performance analysis, otherwise use default.␊
*/␊
#define CONFIG_L2_CACHE␉␉␉/* toggle L2 cache */␊
#define CONFIG_BTB␉␉␉/* toggle branch predition */␊
#define CONFIG_ADDR_STREAMING␉␉/* toggle addr streaming */␊
␊
#define CONFIG_BOARD_EARLY_INIT_F␉1␉/* Call board_pre_init */␊
␊
#undef␉CFG_DRAM_TEST␉␉␉/* memory test, takes time */␊
#define CFG_MEMTEST_START␉0x00000000␉/* memtest region */␊
#define CFG_MEMTEST_END␉␉0x10000000␊
␊
/*␊
* Base addresses -- Note these are effective addresses where the␊
* actual resources get mapped (not physical addresses)␊
*/␊
#define CFG_CCSRBAR_DEFAULT␉0xFF700000␉/* CCSRBAR Default */␊
#define CFG_CCSRBAR␉␉0xE0000000␉/* relocated CCSRBAR */␊
#define CFG_IMMR␉␉CFG_CCSRBAR␉/* PQII uses CFG_IMMR */␊
␊
/*␊
* DDR Setup␊
*/␊
#define CFG_DDR_SDRAM_BASE␉0x00000000␉/* DDR is system memory*/␊
#define CFG_SDRAM_BASE␉␉CFG_DDR_SDRAM_BASE␊
␊
#if defined(CONFIG_SPD_EEPROM)␊
/*␊
* Determine DDR configuration from I2C interface.␊
*/␊
#define SPD_EEPROM_ADDRESS␉0x51␉␉/* DDR DIMM */␊
␊
#else␊
/*␊
* Manually set up DDR parameters␊
*/␊
#define CFG_SDRAM_SIZE␉512␉␉/* DDR is 256MB */␊
#define CFG_DDR_CS0_BNDS␉0x0000001f␉/* 0-256MB */␊
#define CFG_DDR_CS0_CONFIG␉0x80000102␊
#define CFG_DDR_TIMING_1␉0x47445331␊
#define CFG_DDR_TIMING_2␉0x00000800␉/* P9-45,may need tuning */␊
#define CFG_DDR_CONTROL␉0xc2000000␉/* unbuffered,no DYN_PWR */␊
#define CFG_DDR_MODE␉0x40020062␉/* DLL,normal,seq,4/2.5 */␊
#define CFG_DDR_INTERVAL␉0x05160100␉/* autocharge,no open page */␊
#endif␊
␊
/*␊
* Flash on the Local Bus␊
*/␊
#define CFG_LBC_FLASH_BASE␉0xfe000000␉/* Localbus SDRAM */␊
#define CFG_LBC_FLASH_SIZE␉32␉␉/* LBC SDRAM is 32MB */␊
␊
#define CFG_FLASH_BASE␉␉CFG_LBC_FLASH_BASE␉/* start of FLASH 32M */␊
#define CFG_BR0_PRELIM␉␉0xfe001801␉/* port size 32bit */␊
␊
#define CFG_OR0_PRELIM␉␉0xfe000040␉/* 32MB Flash */␊
#define CFG_MAX_FLASH_BANKS␉1␉␉/* number of banks */␊
#define CFG_MAX_FLASH_SECT␉256␉␉/* sectors per device */␊
#undef␉CFG_FLASH_CHECKSUM␊
#define CFG_FLASH_ERASE_TOUT␉60000␉/* Flash Erase Timeout (ms) */␊
#define CFG_FLASH_WRITE_TOUT␉500␉/* Flash Write Timeout (ms) */␊
␊
#define CFG_MONITOR_BASE␉TEXT_BASE␉/* start of monitor */␊
␊
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)␊
#define CFG_RAMBOOT␊
#else␊
#undef␉CFG_RAMBOOT␊
#endif␊
␊
#define CFG_FLASH_CFI_DRIVER␊
#define CFG_FLASH_CFI␊
#define CFG_FLASH_EMPTY_INFO␊
␊
#define CFG_LBC_LCRR␉␉0x00030008 /* LB clock ratio reg */␊
#define CFG_LBC_LBCR␉␉0x00000000 /* LB config reg */␊
#define CFG_LBC_LSRT␉␉0x20000000 /* LB sdram refresh timer */␊
#define CFG_LBC_MRTPR␉␉0x20000000 /* LB refresh timer prescal*/␊
␊
/*␊
* LSDMR masks␊
*/␊
#define CFG_LBC_LSDMR_RFEN␉(1 << (31 - 1))␊
#define CFG_LBC_LSDMR_BSMA1516␉(3 << (31 - 10))␊
#define CFG_LBC_LSDMR_BSMA1617␉(4 << (31 - 10))␊
#define CFG_LBC_LSDMR_RFCR5␉(3 << (31 - 16))␊
#define CFG_LBC_LSDMR_RFCR16␉(7 << (31 - 16))␊
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))␊
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))␊
#define CFG_LBC_LSDMR_ACTTORW3␉(3 << (31 - 22))␊
#define CFG_LBC_LSDMR_ACTTORW7␉(7 << (31 - 22))␊
#define CFG_LBC_LSDMR_ACTTORW6␉(6 << (31 - 22))␊
#define CFG_LBC_LSDMR_BL8␉(1 << (31 - 23))␊
#define CFG_LBC_LSDMR_WRC2␉(2 << (31 - 27))␊
#define CFG_LBC_LSDMR_WRC4␉(0 << (31 - 27))␊
#define CFG_LBC_LSDMR_BUFCMD␉(1 << (31 - 29))␊
#define CFG_LBC_LSDMR_CL3␉(3 << (31 - 31))␊
␊
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))␊
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))␊
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))␊
#define CFG_LBC_LSDMR_OP_MRW␉(3 << (31 - 4))␊
#define CFG_LBC_LSDMR_OP_PRECH␉(4 << (31 - 4))␊
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))␊
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))␊
#define CFG_LBC_LSDMR_OP_RWINV␉(7 << (31 - 4))␊
␊
#define CFG_LBC_LSDMR_COMMON␉( CFG_LBC_LSDMR_BSMA1516␉\␊
␉␉␉␉| CFG_LBC_LSDMR_RFCR5␉␉\␊
␉␉␉␉| CFG_LBC_LSDMR_PRETOACT3␉\␊
␉␉␉␉| CFG_LBC_LSDMR_ACTTORW3␉\␊
␉␉␉␉| CFG_LBC_LSDMR_BL8␉␉\␊
␉␉␉␉| CFG_LBC_LSDMR_WRC2␉␉\␊
␉␉␉␉| CFG_LBC_LSDMR_CL3␉␉\␊
␉␉␉␉| CFG_LBC_LSDMR_RFEN␉␉\␊
␉␉␉␉)␊
␊
/*␊
* SDRAM Controller configuration sequence.␊
*/␊
#define CFG_LBC_LSDMR_1␉␉( CFG_LBC_LSDMR_COMMON \␊
␉␉␉␉| CFG_LBC_LSDMR_OP_PCHALL)␊
#define CFG_LBC_LSDMR_2␉␉( CFG_LBC_LSDMR_COMMON \␊
␉␉␉␉| CFG_LBC_LSDMR_OP_ARFRSH)␊
#define CFG_LBC_LSDMR_3␉␉( CFG_LBC_LSDMR_COMMON \␊
␉␉␉␉| CFG_LBC_LSDMR_OP_ARFRSH)␊
#define CFG_LBC_LSDMR_4␉␉( CFG_LBC_LSDMR_COMMON \␊
␉␉␉␉| CFG_LBC_LSDMR_OP_MRW)␊
#define CFG_LBC_LSDMR_5␉␉( CFG_LBC_LSDMR_COMMON \␊
␉␉␉␉| CFG_LBC_LSDMR_OP_NORMAL)␊
␊
#define CONFIG_L1_INIT_RAM␊
#define CFG_INIT_RAM_LOCK␉1␊
#define CFG_INIT_RAM_ADDR␉0xe4010000␉/* Initial RAM address */␊
#define CFG_INIT_RAM_END␉0x4000␉␉/* End of used area in RAM */␊
␊
#define CFG_GBL_DATA_SIZE␉128␉␉/* num bytes initial data */␊
#define CFG_GBL_DATA_OFFSET␉(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)␊
#define CFG_INIT_SP_OFFSET␉CFG_GBL_DATA_OFFSET␊
␊
#define CFG_MONITOR_LEN␉␉(256 * 1024)␉/* Reserve 256 kB for Mon */␊
#define CFG_MALLOC_LEN␉␉(128 * 1024)␉/* Reserved for malloc */␊
␊
/* Serial Port */␊
#define CONFIG_CONS_ON_SCC /* define if console on SCC */␊
#undef CONFIG_CONS_NONE /* define if console on something else */␊
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */␊
␊
#define CONFIG_BAUDRATE 115200␊
␊
#define CFG_BAUDRATE_TABLE \␊
␉{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}␊
␊
/* Use the HUSH parser */␊
#define CFG_HUSH_PARSER␊
#ifdef␉CFG_HUSH_PARSER␊
#define CFG_PROMPT_HUSH_PS2 "> "␊
#endif␊
␊
/* I2C */␊
#define␉ CONFIG_HARD_I2C␉␉/* I2C with hardware support*/␊
#undef␉CONFIG_SOFT_I2C␉␉␉/* I2C bit-banged */␊
#define CFG_I2C_SPEED␉␉400000␉/* I2C speed and slave address */␊
#define CFG_I2C_SLAVE␉␉0x7F␊
#define CFG_I2C_NOPROBES␉{0x69}␉/* Don't probe these addrs */␊
␊
/* RapidIO MMU */␊
#define CFG_RIO_MEM_BASE␉0xc0000000␉/* base address */␊
#define CFG_RIO_MEM_PHYS␉CFG_RIO_MEM_BASE␊
#define CFG_RIO_MEM_SIZE␉0x20000000␉/* 128M */␊
␊
/*␊
* General PCI␊
* Addresses are mapped 1-1.␊
*/␊
#define CFG_PCI1_MEM_BASE␉0x80000000␊
#define CFG_PCI1_MEM_PHYS␉CFG_PCI1_MEM_BASE␊
#define CFG_PCI1_MEM_SIZE␉0x20000000␉/* 512M */␊
#define CFG_PCI1_IO_BASE␉0xe2000000␊
#define CFG_PCI1_IO_PHYS␉CFG_PCI1_IO_BASE␊
#define CFG_PCI1_IO_SIZE␉0x1000000␉/* 16M */␊
␊
#if defined(CONFIG_PCI)␊
␊
#define CONFIG_NET_MULTI␊
#define CONFIG_PCI_PNP␉␉␉/* do pci plug-and-play */␊
␊
#undef CONFIG_EEPRO100␊
#undef CONFIG_TULIP␊
␊
#if !defined(CONFIG_PCI_PNP)␊
#define PCI_ENET0_IOADDR␉0xe0000000␊
#define PCI_ENET0_MEMADDR␉0xe0000000␊
#define PCI_IDSEL_NUMBER␉0x0c␉/* slot0->3(IDSEL)=12->15 */␊
#endif␊
␊
#undef CONFIG_PCI_SCAN_SHOW␉␉/* show pci devices on startup */␊
#define CFG_PCI_SUBSYS_VENDORID 0x1057␉/* Motorola */␊
␊
#endif␉/* CONFIG_PCI */␊
␊
␊
#if defined(CONFIG_TSEC_ENET)␊
␊
#ifndef CONFIG_NET_MULTI␊
#define CONFIG_NET_MULTI␉1␊
#endif␊
␊
#define CONFIG_MII␉␉1␉/* MII PHY management */␊
#define CONFIG_MPC85XX_TSEC2␉1␊
#define TSEC2_PHY_ADDR␉␉1␊
#define TSEC2_PHYIDX␉␉0␊
␊
#define CONFIG_ETHER_ON_FCC␊
#define CONFIG_ETHER_ON_FCC3␊
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)␊
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)␊
#define CFG_CPMFCR_RAMTYPE 0␊
#define CFG_FCC_PSMR (FCC_PSMR_FDE)␊
␊
#define CONFIG_ETHPRIME␉␉"ENET1"␊
␊
#endif␉/* CONFIG_TSEC_ENET */␊
␊
␊
/*␊
* Environment␊
*/␊
#ifndef CFG_RAMBOOT␊
#define CFG_ENV_IS_IN_FLASH␉1␊
#define CFG_ENV_ADDR␉␉(CFG_MONITOR_BASE - 0x20000)␊
#define CFG_ENV_SECT_SIZE␉0x20000 /* 128K(one sector) for env */␊
#define CFG_ENV_SIZE␉␉0x2000␊
#define CFG_ENV_OFFSET_REDUND␉(CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)␊
#define CFG_ENV_SIZE_REDUND␉(CFG_ENV_SIZE)␊
#else␊
#define CFG_NO_FLASH␉␉1␉/* Flash is not usable now */␊
#define CFG_ENV_IS_NOWHERE␉1␉/* Store ENV in memory only */␊
#define CFG_ENV_ADDR␉␉(CFG_MONITOR_BASE - 0x1000)␊
#define CFG_ENV_SIZE␉␉0x2000␊
#endif␊
␊
#define CONFIG_LOADS_ECHO␉1␉/* echo on for serial download */␊
#define CFG_LOADS_BAUD_CHANGE␉1␉/* allow baudrate change */␊
␊
#define␉CONFIG_TIMESTAMP␉␉/* Print image info with timestamp */␊
␊
#if defined(CFG_RAMBOOT)␊
# define CONFIG_CMD_PRIV␉(CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))␊
#else␊
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL␉| \␊
␉␉␉␉CFG_CMD_DHCP␉| \␊
␉␉␉␉CFG_CMD_NFS␉| \␊
␉␉␉␉CFG_CMD_SNTP␉)␊
#endif␊
␊
#if defined(CONFIG_PCI)␊
# define ADD_PCI_CMD␉␉(CFG_CMD_PCI)␊
#else␊
# define ADD_PCI_CMD␉␉0␊
#endif␊
␊
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV␉| \␊
␉␉␉␉ADD_PCI_CMD␉| \␊
␉␉␉␉CFG_CMD_I2C␉| \␊
␉␉␉␉CFG_CMD_PING␉)␊
#include <cmd_confdefs.h>␊
␊
#undef CONFIG_WATCHDOG␉␉␉/* watchdog disabled */␊
␊
/*␊
* Miscellaneous configurable options␊
*/␊
#define CFG_LONGHELP␉␉␉/* undef to save memory */␊
#define CFG_LOAD_ADDR␉0x2000000␉/* default load address */␊
#define CFG_PROMPT␉"=> "␉␉/* Monitor Command Prompt */␊
␊
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)␊
#define CFG_CBSIZE␉1024␉␉/* Console I/O Buffer Size */␊
#else␊
#define CFG_CBSIZE␉256␉␉/* Console I/O Buffer Size */␊
#endif␊
␊
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */␊
#define CFG_MAXARGS␉16␉␉/* max number of command args */␊
#define CFG_BARGSIZE␉CFG_CBSIZE␉/* Boot Argument Buffer Size */␊
#define CFG_HZ␉␉1000␉␉/* decrementer freq: 1ms ticks */␊
␊
/*␊
* For booting Linux, the board info and command line data␊
* have to be in the first 8 MB of memory, since this is␊
* the maximum mapped by the Linux kernel during initialization.␊
*/␊
#define CFG_BOOTMAPSZ␉(8 << 20)␉/* Initial Memory map for Linux*/␊
␊
/* Cache Configuration */␊
#define CFG_DCACHE_SIZE␉␉32768␊
#define CFG_CACHELINE_SIZE␉32␊
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)␊
#define CFG_CACHELINE_SHIFT␉5␉/*log base 2 of the above value*/␊
#endif␊
␊
/*␊
* Internal Definitions␊
*␊
* Boot Flags␊
*/␊
#define BOOTFLAG_COLD␉0x01␉␉/* Normal Power-On: Boot from FLASH */␊
#define BOOTFLAG_WARM␉0x02␉␉/* Software reboot */␊
␊
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)␊
#define CONFIG_KGDB_BAUDRATE␉230400␉/* speed to run kgdb serial port */␊
#define CONFIG_KGDB_SER_INDEX␉2␉/* which serial port to use */␊
#endif␊
␊
␊
#define CONFIG_LOADADDR␉ 200000 /* default location for tftp and bootm */␊
␊
#define CONFIG_BOOTDELAY 5␉/* -1 disables auto-boot */␊
␊
#define CONFIG_BAUDRATE 115200␊
␊
#define CONFIG_PREBOOT␉"echo;"␉\␊
␉"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \␊
␉"echo"␊
␊
#undef␉CONFIG_BOOTARGS␉␉/* the boot command will set bootargs */␊
␊
#define␉CONFIG_EXTRA_ENV_SETTINGS␉␉␉␉␉\␊
␉"netdev=eth0\0"␉␉␉␉␉␉␉\␊
␉"consdev=ttyS0\0"␉␉␉␉␉␉\␊
␉"nfsargs=setenv bootargs root=/dev/nfs rw "␉␉␉\␊
␉␉"nfsroot=$serverip:$rootpath\0"␉␉␉␉\␊
␉"ramargs=setenv bootargs root=/dev/ram rw\0"␉␉␉\␊
␉"addip=setenv bootargs $bootargs "␉␉␉␉\␊
␉␉"ip=$ipaddr:$serverip:$gatewayip:$netmask"␉␉\␊
␉␉":$hostname:$netdev:off panic=1\0"␉␉␉\␊
␉"addcons=setenv bootargs $bootargs "␉␉␉␉\␊
␉␉"console=$consdev,$baudrate\0"␉␉␉␉\␊
␉"flash_nfs=run nfsargs addip addcons;"␉␉␉␉\␊
␉␉"bootm $kernel_addr\0"␉␉␉␉␉\␊
␉"flash_self=run ramargs addip addcons;"␉␉␉␉\␊
␉␉"bootm $kernel_addr $ramdisk_addr\0"␉␉␉\␊
␉"net_nfs=tftp $loadaddr $bootfile;"␉␉␉␉\␊
␉␉"run nfsargs addip addcons;bootm\0"␉␉␉\␊
␉"rootpath=/opt/eldk/ppc_85xx\0"␉␉␉␉␉\␊
␉"bootfile=/tftpboot/tqm8560/uImage\0"␉␉␉␉\␊
␉"kernel_addr=FE000000\0"␉␉␉␉␉\␊
␉"ramdisk_addr=FE100000\0"␉␉␉␉␉\␊
␉""␊
#define CONFIG_BOOTCOMMAND␉"run flash_self"␊
␊
#endif␉/* __CONFIG_H */␊

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