Clocks, dividers and timers (by P. Boddie)
The clocks provided by the JZ4730 drive the CPU and peripherals. Various sources for these clocks exist:
- External clock, referred to as EXCLK or
EXTAL, 3686400Hz for the Minibook - Real-time clock, referred to as RTCLK,
EXTAL2orRTC, 32768Hz generally - LCD_PCLK is an alternative source for the LCD pixel clock
- USB_CLK is an alternative source, typically 48MHz, for the USB clock
EXCLK is supplied to a phase-locked loop (PLL) to produce other frequencies through input division, feedback division (more like multiplication), and output division. The generated frequency is then divided for different peripherals.
The different products in the JZ4700-series often seem to employ different clock relationships. The JZ4730 differs from the more widely-supported JZ4740-based products in a number of ways.
Clocks
| Clock | JZ4730 | JZ4740 |
|---|---|---|
| AHB (hclock) | PLLEN ? PLL/div : EXCLK | PLL/div |
| APB (pclock) | PLLEN ? PLL/div : EXCLK | PLL/div |
| CPU | PLLEN ? PLL/div : EXCLK | PLL/div |
| I2S | I2CS ? PLL/2 : PLL | I2CS ? source/div : EXCLK |
| LCD device | PLLEN ? PLL/div : EXCLK | source/div |
| LCD pixel | LCD ? LCD_PCLK : PLL/div | source/div |
| Memory | PLLEN ? PLL/div : EXCLK | PLL/div |
| MSC | MSC ? 24000000 : 16000000 | source/div |
| PLL2 (source) | PLL | PLL/div |
| RTC | RTCLK | (as JZ4730) |
| SSI | SSI ? USB_CLK : EXCLK | PLL/div |
| UART | EXCLK | (as JZ4730) |
| USB | UCS ? USB_CLK : PLL/div | UCS ? source : EXCLK |
Above, "div" refers to the clock-specific divider in each case. In the JZ4740 entries, "source" refers to the PLL2 clock output, acting as the source for various other clocks. On the JZ4730 there is apparently no equivalent source, although the I2S clock does appear to employ a similarly divided PLL output.
Clocks are configured using the clock and power management (CPM) registers, of which the following are mentioned above:
- PLLEN is the
CPM_PLCR1_PLL1ENfield (CPM_CPPCR_PLLENon the JZ4740). - I2CS is the
CPM_CFCR_I2Sfield (CPM_CPCCR_I2Son the JZ4740). - MSC is the
CPM_CFCR_MSCfield.
See below for a description of these registers.
Note that according to the vendor code, dividers do not tend to be applied to input frequencies in the JZ4730 when the PLL is not enabled. This is different from the JZ4740 where such inputs are almost always divided regardless of the PLL condition. The JZ4730 documentation also suggests that dividers are always employed.
Dividers
| Divider | JZ4730 | JZ4740 |
|---|---|---|
| Multiplier | n + 2 | (as JZ4730) |
| Input | n + 2 | (as JZ4730) |
| Output | od[n] | (as JZ4730) |
| AHB (hclock) | cd[n] | (as JZ4730) |
| APB (pclock) | cd[n] | (as JZ4730) |
| CPU | cd[n] | (as JZ4730) |
| I2S | 1 | n + 1 |
| LCD device | n + 1 | n + 1 |
| LCD pixel | n + 1 | (as JZ4730) |
| Memory | cd[n] | (as JZ4730) |
| MSC | 1 | n + 1 |
| PLL2 (source) | 1 | PCS ? 1 : 2 |
| USB | n + 1 | (as JZ4730) |
Above, "n" refers to the stored value, with the result providing the chosen value for each divider. The following sequences define certain divider values:
- od = [1, 2, 2, 4]
- cd = [1, 2, 3, 4, 6, 8, 12, 16, 24, 32]
Legacy JZ4730 code employs the cd divider table for the LCD device clock, but the documentation states that it is a linear divider scale.
PCS is the CPM_CPCCR_PCS field (on the JZ4740).
Clock and Power Management Registers
The most important CPM registers are arranged as follows:
| Register | Offset | Purpose |
|---|---|---|
| CFCR | 0x00 | Clock control (CPCCR in JZ4740) |
| PLCR1 | 0x10 | PLL control (CPPCR in JZ4740) |
| MSCR | 0x20 | Clock gate (CLKGR in JZ4740) |
| CFCR2 | 0x60 | LCD pixel frequency divider |
CFCR
The clock control register (CFCR) is arranged as follows:
| Bits | Field | Purpose |
|---|---|---|
| 31 | SSI | SSI clock source |
| 30 | LCS | LCD pixel clock source |
| 29 | I2CS | I2S clock source |
| 28 | UCS | USB clock source |
| 27..25 | UFR | USB divider (when UCS is clear) |
| 24 | MCS | MSC clock source |
| 23 | (Reserved, appears as CKOEN2 in some sources) | |
| 22 | SCLKOEN | SCLKO enable (appears as CKOEN1 in some sources) |
| 21 | (Reserved) | |
| 20 | UPE | Change enable |
| 19..16 | MFR | Memory divider |
| 15..12 | LFR | LCD device clock divider |
| 11..8 | PFR | APB/pclock divider |
| 7..4 | HFR | AHB/hclock divider (appears as SFR in some sources) |
| 3..0 | IFR | CPU divider |
SCLK, enabled by SCLKOEN, is the SDRAM clock output.
PLCR1
| Bits | Field | Purpose |
|---|---|---|
| 31..23 | PLL1FD | PLL multiplier |
| 22..18 | PLL1RD | PLL input division |
| 17..16 | PLL1OD | PLL output division |
| 15..11 | (Reserved) | |
| 10 | PLL1S | PLL stable |
| 9 | PLL1BP | PLL bypass |
| 8 | PLL1EN | PLL enabled |
| 7..0 | PLL1ST | PLL stabilise time (in RTC clock cycles, default 9 cycles) |
PLL1FD uses the range 0..511 to encode multipliers of 2..513.
PLL1RD uses the range 0..31 to encode dividers of 2..33.
PLL1OD employs the following encoding:
| Value | Divider |
|---|---|
| 0 | 1 |
| 1 | 2 |
| 2 | 2 |
| 3 | 4 |
The PLL output frequency is calculated as being...
(EXCLK * multiplier / input division) / output division
Or, in terms of the field values:
(EXCLK * (PLL1FD + 2) / (PLL1RD + 2)) / od[PLL1OD]
MSCR
| Bits | Field | Purpose |
|---|---|---|
| 31..26 | (Reserved) | |
| 25 | UPRT | |
| 24 | UDC | USB device controller |
| 23 | CIM | Camera interface module |
| 22 | KBC | Keyboard controller |
| 21 | EMAC | Ethernet |
| 20 | UART3 | UART #3 |
| 19 | (Reserved) | |
| 18 | AIC | AC97/I2S bit clock (bitclk) |
| 17..15 | (Reserved) | |
| 14 | SCC | Smartcard |
| 13 | MSC | MMC/SD |
| 12 | SSI | SSI/SPI |
| 11 | PWM1 | PWM #1 |
| 10 | PWM0 | PWM #0 |
| 9 | AIC | AC97/I2S peripheral clock (pclk) |
| 8 | I2C | I2C |
| 7 | LCD | LCD controller |
| 6 | UHC | USB host controller |
| 5 | DMAC | DMA controller |
| 4 | (Reserved) | |
| 3 | OST | Operating system timer |
| 2 | UART2 | UART #2 |
| 1 | UART1 | UART #1 |
| 0 | UART0 | UART #0 |
CFCR2
| Bits | Purpose |
|---|---|
| 31..9 | |
| 8..0 | LCD pixel frequency divider (PXFR) |
Timers
Timers are actually peripherals and are not, as such, the same as the clocks described above. However, they are obviously driven by those clocks.
| Timer | JZ4730 | JZ4740 |
|---|---|---|
| OST | (controlled by OST_TCSR) | |
| TCU | (controlled by TCU_TCSR) | |
| WDT | RTC_CLK ? 32768 : EXCLK/128 | (controlled by WDT_TCSR) |
RTC_CLK is the CPM_OCR_EXT_RTC_CLK field.
OST_TCSR registers differ from the JZ4740 TCU_TCSR and WDT_TCSR registers by providing a different set of prescale and clock source options:
| OST_TCSR< 2:0 > (CKS) | Input |
|---|---|
| 0 | PCLK/4 |
| 1 | PCLK/16 |
| 2 | PCLK/64 |
| 3 | PCLK/256 |
| 4 | RTCLK |
| 5 | EXCLK |
| 6 | (Reserved) |
| 7 | (Reserved) |
| WDT_TCSR< 5:3 > / TCU_TCSR< 5:3 > (PRESCALE) | Input |
|---|---|
| 0 | in/1 |
| 1 | in/4 |
| 2 | in/16 |
| 3 | in/64 |
| 4 | in/256 |
| 5 | in/1024 |
Above, "in" refers to the timer input defined as follows:
| WDT_TCSR< 2:0 > / TCU_TCSR< 2:0 > | Clock |
|---|---|
| 1 | PCLK (APB/pclock) |
| 2 | RTC |
| 4 | EXCLK |
Operating System Timer Registers
The JZ4730 operating system timer (OST) registers consist of the timer enable register (TER) together with multiple channels of the other registers at multiples of 0x20 above the OST base address (at 0x10002000).
Global registers:
| Register | Offset | Purpose |
|---|---|---|
| TER | 0x00 | Enable |
Timer-specific registers:
| Register | Offset | Purpose |
|---|---|---|
| TRDR | 0x10 | Reload/Limit |
| TCNT | 0x14 | Counter |
| TCSR | 0x18 | Status |
| TCRB | 0x1c | Read data |
Each timer counts down from the reload/limit value, underflowing and causing an IRQ if enabled.
TER
| Bits | Purpose |
|---|---|
| 7..3 | (Reserved) |
| 2 | Timer 2 enable |
| 1 | Timer 1 enable |
| 0 | Timer 0 enable |
TRDR
| Bits | Purpose |
|---|---|
| 31..0 | Reload/limit value |
TCNT
| Bits | Purpose |
|---|---|
| 31..0 | Counter value |
TCSR
| Bits | Field | Purpose |
|---|---|---|
| 15..8 | (Reserved) | |
| 7 | SF | Switch/busy flag |
| 6 | UF | Underflow IRQ flag |
| 5 | UIE | Underflow IRQ enable |
| 4..3 | (Reserved) | |
| 2..0 | CKS | Input clock source |
The input clock (CKS) field is described above for OST_TCSR<2:0> in the clock configuration section for timers.
The IRQ fields concern the condition when the counter wraps around at the limiting value for the timer. To enable interrupts for this condition, the IRQ flag is first cleared, then the IRQ enable bit is set. Acknowledging the interrupt condition involves clearing the IRQ flag.
The following interrupt numbers correspond to timer IRQs:
| Number | Timer |
|---|---|
| 22 | 2 |
| 23 | 1 |
| 24 | 0 |
TCRB
| Bits | Purpose |
|---|---|
| 31..0 | Counter value |
The purpose of this register is apparently to allow the reading of the "correct" counter value, where TCNT may yield an "incorrect" value if RTCLK or EXCLK are being used as the OST input clock.
To read the correct value, under such circumstances, TCNT is read first, and when TCSR.SF becomes clear, TCRB will provide the appropriate counter value.
Watchdog Timer Registers
The JZ4730 situates its watchdog timer registers in a different region (0x10004000) from the JZ4740 (0x10002000) and other SoCs and it also uses a different arrangement.
| Register | Offset | Purpose |
|---|---|---|
| TCSR | 0x00 | Control/status |
| TCNT | 0x04 | Counter |
TCSR
| Bits | Purpose |
|---|---|
| 7..5 | (Reserved) |
| 4 | Enable |
| 3..0 | (Reserved) |
TCNT
| Bits | Purpose |
|---|---|
| 31..0 | Counter value |
Resources
The following files in the vendor kernel code are informative:
- include/asm-mips/mach-jz4730/clock.h (describes frequency calculations and shows multiplier/divider details)
- include/asm-mips/mach-jz4730/ops.h (hardware operations)
- include/asm-mips/mach-jz4730/regs.h (register layouts)
In modern kernels, the following files are pertinent:
- drivers/clk/ingenic/jz4730-cgu.c (clock definitions and relationships)
- drivers/clk/ingenic/tcu.c (timer control unit definitions)
- drivers/watchdog/jz4740_wdt.c (watchdog timer)
- include/dt-bindings/clock/ingenic,sysost.h (clock numbers)
- include/dt-bindings/clock/ingenic,tcu.h (clock numbers)