Letux 400 Hardware


You are looking at an old revision of the page Clocks. This revision was created by Paul Boddie.

Table of Content

Clocks, dividers and timers (by P. Boddie)

The clocks provided by the JZ4730 drive the CPU and peripherals. Various sources for these clocks exist:

  • External clock, referred to as EXTAL, 3686400Hz for the Minibook
  • Real-time clock, referred to as EXTAL2 or RTC, 32768Hz generally

EXTAL is supplied to a phase-locked loop (PLL) to produce other frequencies through input division, feedback division (more like multiplication), and output division. The generated frequency is then divided for different peripherals.

The different products in the JZ-series often seem to employ different clock relationships. The JZ4730 differs from the more widely-supported JZ4740-based products in a number of ways.


Clock JZ4730 JZ4740
AHB (hclock) PLLEN ? PLL/div : EXTAL PLL/div
APB (pclock) PLLEN ? PLL/div : EXTAL PLL/div
I2S I2CS ? PLL/2 : PLL I2CS ? source/div : EXTAL
LCD device PLLEN ? PLL/div : EXTAL source/div
LCD pixel PLL/div source/div
Memory PLLEN ? PLL/div : EXTAL PLL/div
MSC MSC ? 24000000 : 16000000 source/div
PLL2 (source) PLL PLL/div
RTC EXTAL2 (as JZ4730)
UART EXTAL (as JZ4730)
USB !UCS ? PLL/div : 48000000 UCS ? source : EXTAL

Above, "div" refers to the clock-specific divider in each case. In the JZ4740 entries, "source" refers to the PLL2 clock output, acting as the source for various other clocks. On the JZ4730 there is apparently no equivalent source, although the I2S clock does appear to employ a similarly divided PLL output.

  • PLLEN is the CPM_PLCR1_PLL1EN field (CPM_CPPCR_PLLEN on the JZ4740).
  • I2CS is the CPM_CFCR_I2S field (CPM_CPCCR_I2S on the JZ4740).
  • MSC is the CPM_CFCR_MSC field.

Note that according to the vendor code, dividers do not tend to be applied to input frequencies in the JZ4730 when the PLL is not enabled. This is different from the JZ4740 where such inputs are almost always divided regardless of the PLL condition.


Divider JZ4730 JZ4740
Multiplier n + 2 (as JZ4730)
Input n + 2 (as JZ4730)
Output od[n] (as JZ4730)
AHB (hclock) cd[n] (as JZ4730)
APB (pclock) cd[n] (as JZ4730)
CPU cd[n] (as JZ4730)
I2S 1 n + 1
LCD device cd[n] n + 1
LCD pixel n + 1 (as JZ4730)
Memory cd[n] (as JZ4730)
MSC 1 n + 1
PLL2 (source) 1 PCS ? 1 : 2
USB n + 1 (as JZ4730)

Above, "n" refers to the stored value, with the result providing the chosen value for each divider. The following sequences define certain divider values:

  • od = [1, 2, 2, 4]
  • cd = [1, 2, 3, 4, 6, 8, 12, 16, 24, 32]

PCS is the CPM_CPCCR_PCS field (on the JZ4740).


Timer JZ4730 JZ4740
OST (controlled by OST_TCSR)
TCU (controlled by TCU_TCSR)
WDT RTC_CLK ? 32768 : EXTAL/128 (controlled by WDT_TCSR)


OST_TCSR registers differ from the JZ4740 TCU_TCSR and WDT_TCSR registers by providing a different set of prescale and clock source options:

OST_TCSR< 2:0 > (CKS) Input
0 PCLK/4
1 PCLK/16
2 PCLK/64
3 PCLK/256
WDT_TCSR< 5:3 > / TCU_TCSR< 5:3 > (PRESCALE) Input
0 in/1
1 in/4
2 in/16
3 in/64
4 in/256
5 in/1024

Above, "in" refers to the timer input defined as follows:

WDT_TCSR< 2:0 > / TCU_TCSR< 2:0 > Clock
1 PCLK (APB/pclock)


The following files in the vendor kernel code are informative:

  • include/asm-mips/mach-jz4730/clock.h (describes frequency calculations and shows multiplier/divider details)
  • include/asm-mips/mach-jz4730/ops.h (hardware operations)
  • include/asm-mips/mach-jz4730/regs.h (register layouts)

Created: 1 year 8 months ago
by Nikolaus Schaller

Updated: 1 year 1 month ago
by Paul Boddie

Old Revisions