Letux 400 Hardware


You are looking at an old revision of the page Clocks. This revision was created by Paul Boddie.

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Clocks, dividers and timers (by P. Boddie)

The clocks provided by the JZ4730 drive the CPU and peripherals. Various sources for these clocks exist:

  • External clock, referred to as EXCLK or EXTAL, 3686400Hz for the Minibook
  • Real-time clock, referred to as RTCLK, EXTAL2 or RTC, 32768Hz generally
  • LCD_PCLK is an alternative source for the LCD pixel clock
  • USB_CLK is an alternative source, typically 48MHz, for the USB clock

EXCLK is supplied to a phase-locked loop (PLL) to produce other frequencies through input division, feedback division (more like multiplication), and output division. The generated frequency is then divided for different peripherals.

The different products in the JZ4700-series often seem to employ different clock relationships. The JZ4730 differs from the more widely-supported JZ4740-based products in a number of ways.


Clock JZ4730 JZ4740
AHB (hclock) PLLEN ? PLL/div : EXCLK PLL/div
APB (pclock) PLLEN ? PLL/div : EXCLK PLL/div
I2S I2CS ? PLL/2 : PLL I2CS ? source/div : EXCLK
LCD device PLLEN ? PLL/div : EXCLK source/div
LCD pixel LCD ? LCD_PCLK : PLL/div source/div
Memory PLLEN ? PLL/div : EXCLK PLL/div
MSC MSC ? 24000000 : 16000000 source/div
PLL2 (source) PLL PLL/div
RTC RTCLK (as JZ4730)
UART EXCLK (as JZ4730)
USB !UCS ? PLL/div : USBCLK UCS ? source : EXCLK

Above, "div" refers to the clock-specific divider in each case. In the JZ4740 entries, "source" refers to the PLL2 clock output, acting as the source for various other clocks. On the JZ4730 there is apparently no equivalent source, although the I2S clock does appear to employ a similarly divided PLL output.

Clocks are configured using the clock and power management (CPM) registers, of which the following are mentioned above:

  • PLLEN is the CPM_PLCR1_PLL1EN field (CPM_CPPCR_PLLEN on the JZ4740).
  • I2CS is the CPM_CFCR_I2S field (CPM_CPCCR_I2S on the JZ4740).
  • MSC is the CPM_CFCR_MSC field.

See below for a description of these registers.

Note that according to the vendor code, dividers do not tend to be applied to input frequencies in the JZ4730 when the PLL is not enabled. This is different from the JZ4740 where such inputs are almost always divided regardless of the PLL condition.


Divider JZ4730 JZ4740
Multiplier n + 2 (as JZ4730)
Input n + 2 (as JZ4730)
Output od[n] (as JZ4730)
AHB (hclock) cd[n] (as JZ4730)
APB (pclock) cd[n] (as JZ4730)
CPU cd[n] (as JZ4730)
I2S 1 n + 1
LCD device n + 1 n + 1
LCD pixel n + 1 (as JZ4730)
Memory cd[n] (as JZ4730)
MSC 1 n + 1
PLL2 (source) 1 PCS ? 1 : 2
USB n + 1 (as JZ4730)

Above, "n" refers to the stored value, with the result providing the chosen value for each divider. The following sequences define certain divider values:

  • od = [1, 2, 2, 4]
  • cd = [1, 2, 3, 4, 6, 8, 12, 16, 24, 32]

Legacy JZ4730 code employs the cd divider table for the LCD device clock, but the documentation states that it is a linear divider scale.

PCS is the CPM_CPCCR_PCS field (on the JZ4740).

Clock and Power Management Registers

The most important CPM registers are arranged as follows:

Register Offset Purpose
CFCR 0x00 Clock control (CPCCR in JZ4740)
PLCR1 0x10 PLL control (CPPCR in JZ4740)
MSCR 0x20 Clock gate (CLKGR in JZ4740)
CFCR2 0x60 LCD pixel frequency divider


The clock control register (CFCR) is arranged as follows:

Bits Field Purpose
31 SSI SSI clock source
30 LCS LCD pixel clock source
29 I2S I2C clock source
28 UCS USB clock source
27..25 UFR USB divider (when UCS is clear)
24 MCS MSC clock source
23 (Reserved, appears as CKOEN2 in some sources)
22 SCLKOEN SCLKO enable (appears as CKOEN1 in some sources)
21 (Reserved)
20 UPE Change enable
19..16 MFR Memory divider
15..12 LFR LCD device clock divider
11..8 PFR APB/pclock divider
7..4 HFR AHB/hclock divider (appears as SFR in some sources)
3..0 IFR CPU divider

SCLK, enabled by SCLKOEN, is the SDRAM clock output.


Bits Purpose
31..23 PLL multiplier (PLL1FD)
22..18 PLL input division (PLL1RD)
17..16 PLL output division (PLL1OD)
15..11 (Reserved)
10 PLL stable (PLL1S)
9 PLL bypass (PLL1BP)
8 PLL enabled (PLL1EN)
7..0 PLL1ST


Bits Field Purpose
31..26 (Reserved)
24 UDC USB device controller
23 CIM Camera interface module
22 KBC Keyboard controller
21 EMAC Ethernet
20 UART3 UART #3
19 (Reserved)
18 AIC AC97/I2S bit clock (bitclk)
17..15 (Reserved)
14 SCC Smartcard
11 PWM1 PWM #1
10 PWM0 PWM #0
9 AIC AC97/I2S peripheral clock (pclk)
8 I2C I2C
7 LCD LCD controller
6 UHC USB host controller
5 DMAC DMA controller
4 (Reserved)
3 OST Operating system timer


Bits Purpose
8..0 LCD pixel frequency divider (PXFR)


Timers are actually peripherals and are not, as such, the same as the clocks described above. However, they are obviously driven by those clocks.

Timer JZ4730 JZ4740
OST (controlled by OST_TCSR)
TCU (controlled by TCU_TCSR)
WDT RTC_CLK ? 32768 : EXCLK/128 (controlled by WDT_TCSR)


OST_TCSR registers differ from the JZ4740 TCU_TCSR and WDT_TCSR registers by providing a different set of prescale and clock source options:

OST_TCSR< 2:0 > (CKS) Input
0 PCLK/4
1 PCLK/16
2 PCLK/64
3 PCLK/256
6 (Reserved)
7 (Reserved)
WDT_TCSR< 5:3 > / TCU_TCSR< 5:3 > (PRESCALE) Input
0 in/1
1 in/4
2 in/16
3 in/64
4 in/256
5 in/1024

Above, "in" refers to the timer input defined as follows:

WDT_TCSR< 2:0 > / TCU_TCSR< 2:0 > Clock
1 PCLK (APB/pclock)

Operating System Timer Registers

The JZ4730 operating system timer (OST) registers consist of the timer enable register (TER) together with multiple channels of the other registers at multiples of 0x20 above the OST base address (at 0xb0002000).

Global registers:

Register Offset Purpose
TER 0x00 Enable

Timer-specific registers:

Register Offset Purpose
TRDR 0x10 Reload/Limit
TCNT 0x14 Counter
TCSR 0x18 Status
TCRB 0x1c Read data

Each timer counts down from the reload/limit value, underflowing and causing an IRQ if enabled.


Bits Purpose
7..3 (Reserved)
2 Timer 2 enable
1 Timer 1 enable
0 Timer 0 enable


Bits Purpose
31..0 Reload/limit value


Bits Purpose
31..0 Counter value


Bits Field Purpose
15..8 (Reserved)
7 SF Switch/busy flag
6 UF Underflow IRQ flag
5 UIE Underflow IRQ enable
4..3 (Reserved)
2..0 CKS Input clock source

The input clock (CKS) field is described above for OST_TCSR<2:0> in the clock configuration section for timers.

The IRQ fields concern the condition when the counter wraps around at the limiting value for the timer. To enable interrupts for this condition, the IRQ flag is first cleared, then the IRQ enable bit is set. Acknowledging the interrupt condition involves clearing the IRQ flag.

The following interrupt numbers correspond to timer IRQs:

Number Timer
22 2
23 1
24 0


Bits Purpose
31..0 Counter value

The purpose of this register is apparently to allow the reading of the "correct" counter value, where TCNT may yield an "incorrect" value if RTCLK or EXCLK are being used as the OST input clock.

To read the correct value, under such circumstances, TCNT is read first, and when TCSR.SF becomes clear, TCRB will provide the appropriate counter value.

Watchdog Timer Registers

The JZ4730 situates its watchdog timer registers in a different region (0x10004000) from the JZ4740 (0x10002000) and other SoCs and it also uses a different arrangement.

Register Offset Purpose
TCSR 0x00 Control/status
TCNT 0x04 Counter


Bits Purpose
4 Enable


Bits Purpose
31..0 Counter value


The following files in the vendor kernel code are informative:

  • include/asm-mips/mach-jz4730/clock.h (describes frequency calculations and shows multiplier/divider details)
  • include/asm-mips/mach-jz4730/ops.h (hardware operations)
  • include/asm-mips/mach-jz4730/regs.h (register layouts)

In modern kernels, the following files are pertinent:

  • drivers/clk/ingenic/jz4730-cgu.c (clock definitions and relationships)
  • drivers/clk/ingenic/tcu.c (timer control unit definitions)
  • drivers/watchdog/jz4740_wdt.c (watchdog timer)
  • include/dt-bindings/clock/ingenic,sysost.h (clock numbers)
  • include/dt-bindings/clock/ingenic,tcu.h (clock numbers)