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The direct memory access peripheral
DMA
The JZ4730 has a slightly different memory layout for DMA registers compared to the JZ4740 and related SoCs. However, the general base location for the DMA peripheral remains at 0x10020000.
There are two kinds of registers: global and channel. The global registers appear in one location relative to the DMA base address and control the peripheral generally.
| Register | Offset | Purpose |
|---|---|---|
| IRQP | 0xf8 | IRQ pending |
| DMAC | 0xfc | Control |
Note that the order of these is reversed from the JZ4740 which also exposes more global registers.
Meanwhile, channel registers appear in as many locations as there are distinct channels, starting at 0x10020000, with banks of channel registers occurring at intervals of 0x20, with the registers being defined relative to the base of each bank as follows:
| Register | Offset | Purpose |
|---|---|---|
| DSA | 0x00 | Source address |
| DDA | 0x04 | Descriptor address (JZ4740: target address) |
| DTC | 0x08 | Transfer count |
| DRT | 0x0c | Request type |
| DCCSR | 0x10 | Control/status |
Other registers provided by the JZ4740 do not appear to be supported.
Resources
In recent kernels, the DMA support has been located in the following file:
- drivers/dma/dma-jz4780.c