The direct memory access peripheral

DMA

The JZ4730 has a slightly different memory layout for DMA registers compared to the JZ4740 and related SoCs. However, the general base location for the DMA peripheral remains at 0x10020000.

There are two kinds of registers: global and channel. The global registers appear in one location relative to the DMA base address and control the peripheral generally.

Register	Offset	Purpose
IRQP	0xf8	IRQ pending
DMAC	0xfc	Control

Note that the order of these is reversed from the JZ4740 which also exposes more global registers.

Meanwhile, channel registers appear in as many locations as there are distinct channels, starting at 0x10020000. There are 6 channels in the JZ4730 peripheral.

Banks of channel registers occur at intervals of 0x20, with the registers being defined relative to the base of each bank as follows:

Register	Offset	Purpose
DSA	0x00	Source address
DDA	0x04	Descriptor address (JZ4740: target address)
DTC	0x08	Transfer count
DRT/DRS	0x0c	Request type/source
DCS/DCCSR	0x10	Channel command/status

Other registers provided by the JZ4740 do not appear to be supported.

Global Registers

DMAC

Bit	Field	Purpose
0	DME	Enable
2	AER	Test for address error
3	HTR	Test for halt error
8..9	PR	Channel priorities

Channel priorities are indicated in the above field using the following values:

Value	Policy
0	01234567
1	02314675
2	20136457
3	Round robin

The above policies are taken from the legacy JZ4730 definitions. It is not clear whether there really are channels 6 and 7.

Round robin mode (according to JZ4740 documentation) employs two priority levels (channels 0 to 3, channels 4 to 7) with channels being serviced in turn within each level.

IRQP

Bit	Purpose
15..8	IRQ pending for channels

Following the hints in the JZ4740 definitions, it seems likely that bits 13..8 are used to indicate interrupt conditions for channels 5..0.

Channel Registers

DSA

This register holds the 32-bit source address involved in a transfer.

DDA

The descriptor address register is structured as follows:

Bits	Purpose
31..12	Descriptor base address
11..4	Descriptor offset address
3..0	(Zero)

In practice, a descriptor address is just a 32-bit address which must be aligned to a 16-byte boundary.

DRT/DRS

According to the legacy JZ4730 kernel definitions, request sources/types are associated with bits in the DRT register as follows:

Bit	Request Type/Source
0	EXTREXTR
4	PCMCIAOUT
5	PCMCIAIN
8	AUTO
10	DESOUT
11	DESIN
14	UART3OUT
15	UART3IN
16	UART2OUT
17	UART2IN
18	UART1OUT
19	UART1IN
20	UART0OUT
21	UART0IN
22	SSIOUT
23	SSIIN
24	AICOUT
25	AICIN
26	MSCOUT
27	MSCIN
28	OST2

The JZ4740 provides request types 8 and 20-27, plus 28 being TCU, and additionally 29 being SADC and 30 being SLCD.

DCS/DCCSR

The channel command and status register incorporates command settings that appear to be on the dedicated command register (DCMD) in the JZ4740.

Bits	Field	Purpose
31	EACKS
30	EACKM
29..28	ERDM
27	EOPM
23	SAM	Source address increment (set to increment)
22	DAM	Destination address increment (set to increment)
19..16	RDIL	Request detection interval length
15..14	SP/SWDH	Source port width
13..12	DP/DWDH	Destination port width
10..8	DS	Transfer unit data size
7	TM	Block mode
4	AR	Address error occurred
3	TC	Transfer completed
2	HLT	Transfer halted
1	TCIE	Channel IRQ enable
0	CHDE	Channel enable/enabled

Request detection interval length (RDIL) appears to dictate the frequency of transfer events by indicating how ofter, in terms of transfer units, a transfer request condition may be detected and acted upon.

Value	Interval
0	0 (ignored)
1	2
2	4
3	8
4	12
5	16
6	20
7	24
8	28
9	32
10	48
11	60
12	64
13	124
14	128
15	200

Port widths (SWDH and DWDH) employ the following values:

Value	Width
0	32-bit
1	8-bit
2	16-bit
3	(Reserved)

The transfer unit data size is specified using the following values:

Value	Size
0	32-bit
1	8-bit
2	16-bit
3	16-byte
4	32-byte

Block mode dedicates the bus to a transfer whereas single mode (TM cleared) introduces the request detection interval length (RDIL) mechanism, allowing multiplexing of accesses to the bus.

Interrupts

The DMA controller interrupt number applicable to the interrupt controller (INTC) registers is 21. However, there are also channel-level interrupts from 31 to 36.

Resources

In recent kernels, the DMA support has been located in the following file:

• drivers/dma/dma-jz4780.c