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The direct memory access peripheral
DMA
The JZ4730 has a slightly different memory layout for DMA registers compared to the JZ4740 and related SoCs. However, the general base location for the DMA peripheral remains at 0x13020000.
(On the JZ4780, the peripheral is at 0x13420000 with global registers at 0x13421000.)
There are two kinds of registers: global and channel. The global registers appear in one location relative to the DMA base address and control the peripheral generally.
Register | Offset | Purpose |
---|---|---|
IRQP | 0xf8 | IRQ pending |
DMAC | 0xfc | Control |
Note that the order of these is reversed from the JZ4740 which also exposes more global registers.
Meanwhile, channel registers appear in as many locations as there are distinct channels, starting at 0x13020000. There are 6 channels in the JZ4730 peripheral.
Banks of channel registers occur at intervals of 0x20, with the registers being defined relative to the base of each bank as follows:
Register | Offset | Purpose |
---|---|---|
DSA | 0x00 | Source address |
DTA/DDA | 0x04 | Target/destination address |
DTC | 0x08 | Transfer count |
DRT/DRS | 0x0c | Request type/source |
DCS/DCCSR | 0x10 | Channel control/status |
Other registers provided by the JZ4740 do not appear to be supported.
Global Registers
DMAC
Bit | Field | Purpose |
---|---|---|
31..10 | (Reserved) | |
9..8 | PM/PR | Channel priority mode |
7..4 | (Reserved) | |
3 | HLT/HTR | Halt error occurred |
2 | AR/AER | Address error occurred |
0 | DMAE/DME | Enable DMA |
Channel priorities are indicated in the above field using the following values:
Value | Prioritisation |
---|---|
0 | 0 > 1 > 2 > 3 > 4 > 5 > 6 > 7 |
1 | 0 > 2 > 3 > 1 > 4 > 6 > 7 > 5 |
2 | 2 > 0 > 1 > 3 > 6 > 4 > 5 > 7 |
3 | Round robin |
The above policies are taken from the legacy JZ4730 definitions. Since there are apparently no channels 6 and 7, these channels should presumably be ignored when considering the above prioritisation schemes.
Round robin mode employs two priority levels (channels 0 to 3, channels 4 to 7) with channels being serviced in turn within each level and with the upper level always having priority over the lower level.
IRQP
Bit | Purpose |
---|---|
31..16 | (Reserved) |
15 | IRQ pending (channel 0) |
14 | IRQ pending (channel 1) |
13 | IRQ pending (channel 2) |
12 | IRQ pending (channel 3) |
11 | IRQ pending (channel 4) |
10 | IRQ pending (channel 5) |
9 | IRQ pending (channel 6) |
8 | IRQ pending (channel 7) |
7..0 | (Reserved) |
This appears to be different to how the JZ4740 arranges the channel IRQ pending bits (employing a direct correspondence between channel numbers and bit numbers).
Channel Registers
DSA
This register holds the 32-bit source address involved in a transfer.
DTA/DDA
This register holds the 32-bit destination/target address involved in a transfer.
DTC
Bits | Purpose |
---|---|
31..24 | (Reserved) |
23..0 | Transfer count |
DRT/DRS
Bits | Purpose |
---|---|
31..5 | (Reserved) |
4..0 | Transfer request type |
Request sources/types are associated with bits in the DRT register as follows:
Value | Request Type/Source | Transfer Condition |
---|---|---|
0 | External request | DREQ0/1 pin |
1..3 | (Reserved) | |
4 | Memory to PCMCIA | |
5 | PCMCIA to memory | |
6..7 | (Reserved) | |
8 | Auto-request | (See note) |
10 | Memory to DES | |
11 | DES to memory | |
14 | Memory to UART3 | Transmit FIFO empty |
15 | UART3 to memory | Receive FIFO full |
16 | Memory to UART2 | Transmit FIFO empty |
17 | UART2 to memory | Receive FIFO full |
18 | Memory to UART1 | Transmit FIFO empty |
19 | UART1 to memory | Receive FIFO full |
20 | Memory to UART0 | Transmit FIFO empty |
21 | UART0 to memory | Receive FIFO full |
22 | Memory to SSI | Transmit FIFO empty |
23 | SSI to memory | Receive FIFO full |
24 | Memory to AIC | Transmit FIFO empty |
25 | AIC to memory | Receive FIFO full |
26 | Memory to MSC | Transmit FIFO empty |
27 | MSC to memory | Receive FIFO full |
28 | OST2 memory to memory | OST underflow/wraparound |
External requests involve the DREQ0/1 and DACK0/1 pins.
The JZ4740 provides request types 8 and 20-27, plus 28 being TCU, and additionally 29 being SADC and 30 being SLCD.
When request type 8 (AUTO) is used, enabling a channel using DCCSR.CHDE (and having DMA enabled globally using DMAC.DME) causes the transfer to occur. Otherwise, requests are initiated by the indicated peripherals.
DCS/DCCSR
The channel command and status register incorporates command settings that appear to be on the dedicated command register (DCMD) in the JZ4740.
Bits | Field | Purpose |
---|---|---|
31 | EACKS | External DMA DACKn output polarity |
30 | EACKM | External DMA DACKn output mode |
29..28 | ERDM | External DMA request detection mode |
27 | EOPM | External DMA end of process mode |
26..24 | (Reserved) | |
23 | SAI/SAM | Source address increment (set to increment) |
22 | DAI/DAM | Destination address increment (set to increment) |
21..20 | (Reserved) | |
19..16 | RDIL | Request detection interval length |
15..14 | SP/SWDH | Source port width |
13..12 | DP/DWDH | Destination port width |
11 | (Reserved) | |
10..8 | TSZ/DS | Transfer unit data size |
7 | TM | Transfer mode (unset: single; set: block) |
6..5 | (Reserved) | |
4 | AR | Address error occurred |
3 | TT/TC | Transfer completed |
2 | HLT | Transfer halted |
1 | TIE/TCIE | Channel IRQ enable |
0 | CTE/CHDE | Channel enable/enabled |
The output mode select (EACKM) field appears to be used for writes to peripherals in the legacy kernel code, although since EACKM concerns external transfers, this may be superfluous in many situations.
The EACKS and EOPM fields employ the following values:
Value | Mode |
---|---|
0 | Active high |
1 | Active low |
The EACKM field employs the following values:
Value | Mode |
---|---|
0 | DACK output on read cycle |
1 | DACK output on write cycle |
The request detection mode (ERDM) field employs the following values:
Value | Mode |
---|---|
0 | Low level |
1 | Falling edge |
2 | High level |
3 | Rising edge |
Request detection interval length (RDIL) appears to dictate the frequency of transfer events by indicating how ofter, in terms of transfer units, a transfer request condition may be detected and acted upon.
Value | Interval |
---|---|
0 | 0 (ignored) |
1 | 2 |
2 | 4 |
3 | 8 |
4 | 12 |
5 | 16 |
6 | 20 |
7 | 24 |
8 | 28 |
9 | 32 |
10 | 48 |
11 | 60 |
12 | 64 |
13 | 124 |
14 | 128 |
15 | 200 |
Port widths (SWDH and DWDH) employ the following values:
Value | Width |
---|---|
0 | 4 bytes (32 bits) |
1 | 1 byte (8 bits) |
2 | 2 bytes (16 bits) |
3 | (Reserved) |
The transfer unit data size is specified using the following values:
Value | Size |
---|---|
0 | 4 bytes (32 bits) |
1 | 1 byte (8 bits) |
2 | 2 bytes (16 bits) |
3 | 16 bytes |
4 | 32 bytes |
Block mode dedicates the bus to a transfer whereas single mode (TM cleared) introduces the request detection interval length (RDIL) mechanism, allowing multiplexing of accesses to the bus.
Descriptors
Other JZ4700-series SoCs support transfer descriptors that follow the layout of the command register, with the lowest five bits being defined as follows:
Bits | Field | Purpose |
---|---|---|
4 | V | Descriptor valid |
3 | VM | Descriptor valid mode |
2 | VIE | Descriptor invalid interrupt enable |
1 | TIE | Transfer interrupt enable |
0 | LINK | Descriptor link enable |
However, the JZ4730 does not provide a separate command register, and it seems as if no provision exists for descriptor-driven transfers.
Interrupts
The DMA controller interrupt number applicable to the interrupt controller (INTC) registers is 21. However, there are also channel-level interrupts from 31 to 36.
Conditions and Operations
A transfer has ceased on a channel if DCS.AR/DCCSR.AR, DCS.TT/DCCSR.TC or DCS.HLT/DCCSR.HLT are set. The corresponding global indication involves the DMAC.AR and DMAC.HLT bits.
Enabling a channel involves clearing the above channel bits, setting the DCCSR.CHDE bit and then setting the DCCSR.TCIE bit.
Examples
The dma.c
and dma.h
files in the legacy kernel provide definitions for various DMA operations, particularly sound-related transfers.
Resources
In recent kernels, the DMA support has been located in the following file:
- drivers/dma/dma-jz4780.c
In the legacy vendor kernel:
- arch/mips/jz4730/dma.c
- linux/include/asm-mips/mach-jz4730/dma.h
- linux/include/asm-mips/mach-jz4730/ops.h
- linux/include/asm-mips/mach-jz4730/regs.h