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GPIO assignment for the JZ4730 inside the Mipsbook
GPIO
The GPIO pins are used on the Letux 400 for things like the status LEDs and to control the LCD backlight. The registers on the JZ4730 are arranged as follows:
| Register | Offset | Purpose |
|---|---|---|
| PxGPDR | 0x00 | Port data |
| PxGPDIR | 0x04 | Port direction |
| PxGPODR | 0x08 | ? |
| PxGPPUR | 0x0c | Pull enable |
| PxGPALR | 0x10 | Port function lower |
| PxGPAUR | 0x14 | Port function upper |
| PxGPDLR | 0x18 | IRQ detect lower |
| PxGPDUR | 0x1c | IRQ detect upper |
| PxGPIER | 0x20 | IRQ enable |
| PxGPFR | 0x28 | IRQ flag |
Here, Px refers to a particular port designation. We may use the following convention indicating the pins exposed by each port and the offset from the start of GPIO memory for each port's registers (described above):
| Px | Port | Pins (Global) | Offset |
|---|---|---|---|
| PA | A | 0..31 | 0x00 |
| PB | B | 32..63 | 0x30 |
| PC | C | 64..95 | 0x60 |
| PD | D | 96..127 | 0x90 |
GPIO memory is located at 0x10010000 in physical memory space.
Since 32 pins are exposed per port, single registers that configure all pins have a direct bit-to-pin correspondence.
Where upper and lower registers exist, the combination of the registers describes all 32 pins:
| Upper: bits 63..32 | Lower: bits 31..0 |
|---|---|
| Pins 31..16 | Pins 15..0 |
Each pin is described by two bits, with pin X therefore employing bits X2 and X2+1. Taken together, these bits encode a value in the range 0..3 for the relevant pin configuration.
Configuration
Unlike other JZ4700-series SoCs, no "set" or "clear" registers are provided. It is therefore necessary to read, update, write when changing a register.
Port Direction
The PxGPDIR register employs bit value 0 for input and IRQ pins, bit value 1 for output pins.
Pull-Up Enable
The PxGPPUR register employs bit value 0 to disable pull-ups on pins, bit value 1 to enable pull-ups.
Port Function
The PxGPALR, PxGPAUR register pair employs pairs of adjacent bits to configure pins:
| Bit Values | Function |
|---|---|
| 00 | GPIO |
| 01 | Alternate function 1 |
| 10 | Alternate function 2 |
| 11 | Alternate function 3 |
Alternate functions are pin-specific and are defined as follows:
| Port | Pins | Function | Peripheral |
|---|---|---|---|
| A | 0..11 | 1 | CIM |
| A | 12..15 | 1 | DMA (1 of 2) |
| A | 16..23 | 1 | UART3 |
| A | 24..25 | 1 | UART1 |
| A | 26..27 | 1 | DMA (2 of 2) |
| A | 28..31 | 1 | USB |
| B | 0..1 | 1 | PS/2 |
| B | 2..7 | 1 | MSC |
| B | 2..15 | 1 | UPRT (1 of 2) |
| B | 8..23 | 1 | LCD (16-bit data) |
| B | 27..31 | 1 | LCD (signalling) |
| B | 24..26 | 1 | LCD (slave) |
| B | 24..26 | 2 | LCD (master) |
| C | 0, 2 | 1 | SCC0 |
| C | 1, 3 | 1 | SCC1 |
| C | 4, 6..7 | 1 | I2S (common) |
| C | 5..7, 13 | 1 | AC97 (1 of 2) |
| C | 8..12 | 1 | SSI |
| C | 13..14 | 1 | I2S (slave) |
| C | 13..14 | 2 | I2S (master) |
| C | 14 | 2 | AC97 (2 of 2) |
| C | 15..23 | 1 | EMC |
| C | 24..29 | 1 | PCMCIA |
| C | 30..31 | 1 | PWM |
| D | 0..14 | 1 | UPRT (2 of 2) |
| D | 15, 29 | 1 | UART2 |
| D | 16..28 | 1 | Ethernet |
| D | 30..31 | 1 | UART0 |
IRQ Detect
The PxGPDLR, PxGPDUR register pair employs pairs of adjacent bits to configure pins:
| Bit Values | Detection Event |
|---|---|
| 00 | Low level |
| 01 | High level |
| 10 | Negative edge/falling level |
| 11 | Positive edge/rising level |
Interrupts
The following mapping applies for interrupts triggered by pin activity:
| Port | IRQ Number |
|---|---|
| A | 28 |
| B | 27 |
| C | 26 |
| D | 25 |
Resources
- u-boot-1.1.6/include/asm-mips/jz4730.h
- GPIOs
In modern kernels, the following files are pertinent:
- drivers/gpio/gpio-ingenic.c
- drivers/pinctrl/pinctrl-ingenic.c