The interrupt controller for the JZ4730.
The interrupt controller (INTC) indicates the presence of interrupt conditions for the hardware peripherals of the JZ4730.
The memory base for the interrupt controller registers is 0x10001000.
|ICMSR||0x08||Interrupt mask set|
|ICMCR||0x0c||Interrupt mask clear|
Unusually for the JZ4730, the mask set (ICMSR) and clear (ICMCR) registers permit the setting of bits in these registers to selectively set and clear bits (respectively) in the mask register (ICMR), thus avoiding read-update-set operations on the mask register itself.
The following common arrangement applies to all registers.
|28||GPIO0||GPIO port A|
|27||GPIO1||GPIO port B|
|26||GPIO2||GPIO port C|
|25||GPIO3||GPIO port D|
|24||OST0||Operating system timer 0 (see Clocks)|
|23||OST1||Operating system timer 1 (see Clocks)|
|22||OST2||Operating system timer 2 (see Clocks)|
|19||ETH||Ethernet MAC controller|
|18||CIM||Camera interface module|
|17||SSI||Synchronous serial interface (SPI)|
|13||UHC||USB host controller|
|12||UDC||USB device controller|
|11||SCC0||Smartcard controller 0|
|10||SCC1||Smartcard controller 1|
|3||UPRT||Micro printer controller|
The sources register indicates interrupt conditions on the different interrupt sources.
Since the interrupt sources tend to be at the peripheral level, further investigation of the precise interrupt condition is required at the peripheral level. For example, the presence of an interrupt on GPIO3 would require the inspection of the IRQ flag register associated with the corresponding GPIO port (PCGPFR) in order to determine which pin has caused an interrupt to occur.
Since software may use masking to ignore interrupt conditions, it is generally more appropriate to test pending interrupts using the pending register (ICPR).
The mask register indicates which sources are masked, with a set bit indicating that the corresponding source is masked and will therefore not produce a pending interrupt condition (in ICPR) or an interrupt request (IRQ).
When handling interrupt requests, the interrupt condition responsible for causing the request may be masked so as to avoid the handler being interrupted by another interrupt of that nature.
The pending register indicates which unmasked interrupt conditions are occurring and thus which interrupt requests are pending.