The LCD controller is practically the same as that used by the JZ4720 and JZ4740.
The LCD panel is signalled using the port B pin groups from 8 to 23 (16-bit data) and 27 to 31 (signalling) set to alternate function 1, and pins 24 to 26 set to alternate function 2 (master).
The panel itself employs a backlight controllable via PWM channel 0, outputting a signal through port C pin 30. The backlight LED is enabled by asserting port C pin 28.
The display is enabled by asserting port C pin 29.
An appropriate PWM configuration for the backlight is the following:
- Duty: 250
- Period: 299
- Prescale: 47
Brightness control involves changing the duty with a minimum value of 0 and a maximum value of 300.
The LCD controller requires clock configuration (see Clocks). The LCD clock supply is enabled and disabled using MSCR.
Two clocks are used by the controller: a "device" clock and a "pixel" clock.
The source of the LCD device clock is the PLL if enabled (in PLCR1), which may be divided further (configured using CFCR). Otherwise, EXCLK is used.
The source of the LCD pixel clock is an alternative clock source if configured (in CFCR) or the PLL divided to give the desired frequency (indicated using CFCR2).