Letux 400 Hardware

MMC

Table of Content

Details of the MMC peripheral

MMC

The JZ4730 has a memory card (MMC) peripheral that appears to be very close, if not identical, to that used in the JZ4740 and other SoCs of that generation. (The JZ4780 and its generation appear to offer various enhancements.)

The base location of the peripheral is at 0x10021000 in physical memory. In various manuals and headers, it is typically referred to as MSC (MMC/SD Controller). The registers appearing at/from this location are as follows:

Register Offset Purpose
STRPCL 0x000 Start/stop control
STAT 0x004 Status
CLKRT 0x008 Clock rate
CMDAT 0x00C Command and data control
RESTO 0x010 Response timeout
RDTO 0x014 Read timeout
BLKLEN 0x018 Block length
NOB 0x01C Number of blocks
SNOB 0x020 Successfully-transferred number of blocks
IMASK 0x024 Interrupt mask
IREG 0x028 Interrupt status
CMD 0x02C Command index
ARG 0x030 Command argument
RES 0x034 Response FIFO
RXFIFO 0x038 Receive data FIFO
TXFIFO 0x03C Transmit data FIFO

STRPCL

Start/stop control permits write-only direction of various operations.

Bit Field Purpose
15..8 (Reserved)
7 EXIT_MULTIPLE Send CMD12 or CMD52 (I/O abort) to terminate multi-block transfer
6 EXIT_TRANSFER SD suspend; MMC terminate stream read
5 START_READWAIT Start SDIO ReadWait
4 STOP_READWAIT Stop SDIO ReadWait
3 RESET Reset controller
2 START_OP Start new operation
1..0 CLOCK_CONTROL Stop MMC clock (01), start MMC clock (10)

STAT

The status register provides various read-only indicators.

Bit Field Purpose
15 IS_RESETTING Reset in progress
14 SDIO_INT_ACTIVE SDIO interrupt detected
13 PRG_DONE Card has finished programming and is not busy
12 DATA_TRAN_DONE Data transmission completed
11 END_CMD_RES Command (and response) completed
10 DATA_FIFO_AFULL Data FIFO is almost full (words received >= 15)
9 IS_READWAIT Card has entered ReadWait state
8 CLK_EN Clock is enabled
7 DATA_FIFO_FULL Data FIFO is full
6 DATA_FIFO_EMPTY Data FIFO is empty
5 CRC_RES_ERR CRC error on response
4 CRC_READ_ERROR CRC error on received data
3..2 CRC_WRITE_ERROR_BIT CRC write error status
1 TIME_OUT_RES Response timed out
0 TIME_OUT_READ Data read timed out

The CRC write error status codes are as follows:

Value Status
0 No error
1 Erroneous transmission
2 No CRC status returned
3 (Reserved)

CLKRT

The clock rate register provides support for dividing the input clock frequency. This frequency is set by the MSC clock input (see the Clocks document) and will be 16MHz or 24MHz.

Bit Field Purpose
15..3 (Reserved)
2..0 CLK_RATE Division of the input clock (CLK_SRC)

The division values are encoded as follows:

Value Division Resultant Clock
0 1 CLK_SRC
1 2 CLK_SRC / 2
2 4 CLK_SRC / 4
3 8 CLK_SRC / 8
4 16 CLK_SRC / 16
5 32 CLK_SRC / 32
6 64 CLK_SRC / 64
7 128 CLK_SRC / 128

Operations

Starting an operation involves setting START_OP and CLOCK_CONTROL to start MMC clock (10).

DMA Usage

To use the DMA peripheral to transfer data via the MMC peripheral, the following DMA registers are used:

DTC is set to the number of transfer units (total size divided by transfer data size)

DCCSR is configured with...

  • source (SWDH) and destination (DWDH) port widths of 32 bits
  • a transfer data size (DS) of 32 bytes
  • single transfer mode (TM)
  • request interval detection length (RDIL) of 0

Created: 1 year 7 months ago
by Paul Boddie

Updated: 1 year 7 months ago
by Paul Boddie

Old Revisions