Comment 1 by Nikolaus Schaller, Jan 26, 2010

Here some analysis of the OMAP3530 programming document
* Chapter 16.2.4.6 Pulse-Width Modulation
* according to 16.3 General-Purpose (GP) Timer Registers
there are 12 instances of the timers to choose from
* each timer has approx. 13 registers to define

  => code will be something like

  struct timer
    {

    }

  struct timer *addr=(struct timer *) 0x4831 8000;  // timer base 
addresses are not evenly distributed!!!
  addr->register = ...

* 7.4.4 Pad Functional Multiplexing and Configuration 
* 16.2.1 GP Timers Overview

  => we have to choose the correct timer! On GTA04E we are 
connected to Timer 10; on GTA04 it will be Timer 11

* Table 16-15. GPTIMER9 to GPTIMER12 Register Summary 
  => base address is 0x4808 6000

Comment 2 by Nikolaus Schaller, Jan 26, 2010

If possible, the Pulse should be synchronized to vsync to avoid 
flicker and moiree patterns.

But: VSNC is approx. 50 Hz while the PWM signal should be approx. 1 
kHz according to the TPS61041 data sheet.

So we may have to rely on the C204 capacity (4.7 uF).

Comment 3 by Nikolaus Schaller, Jan 26, 2010

the required struct already exist in

  include/asm-arm/arch-omap3/cpu.h:struct gptimer {

it is used in

  cpu/arm_cortexa8/omap3/clock.c:	struct gptimer *gpt1_base = 
(struct gptimer *)OMAP34XX_GPT1;
  cpu/arm_cortexa8/omap3/timer.c:static struct gptimer *timer_base = 
(struct gptimer *)CONFIG_SYS_TIMERBASE;

There is also a constant

  include/asm-arm/arch-omap3/omap3.h:#define OMAP34XX_GPT10			
0x48086000


So, everything we need may be reduced to something like

  struct gptimer *gpt_base = (struct gptimer *)OMAP34XX_GPT10; // 
use GPT11 for GTA04
  writel(value, &gpt_base->registername);

And of course setting the MUX.

Note: as written elsewhere we should try to sync the PWM impulse to 
VSYNC of the display (there may be an Interrupt or DMA request input 
for the timer).