Normally, I2C is used for communicating with various peripherals, and since the Power management, RTC and Audio involves communicating with an I2C peripheral, it is likely that support is needed to make that work on the Letux 400.
The peripheral appears to be the same or similar to that provided by the JZ4740.
The device clock for I2C is the pclock or PCLK. See Clocks for details.
Unlike the JZ4780, the JZ4730 employs dedicated pins for I2C communication, not GPIO-controlled pins. These are V5 for SCK (clock) and Y4 for SDA (data).
Interrupts caused by the I2C peripheral are signalled as interrupt number 1 in the various interrupt controller registers (see InterruptController).
The data register (DR) is arranged as follows:
The control register (CR) is arranged as follows:
The start and stop bits respond to set operations only, not clear operations. Presumably, it only makes sense to set one of these at a time.
The status register (SR) is arranged as follows:
|4||STX||FIFO buffer not empty|
|2||TEND||Transaction end flag|
|1||DRF||Data valid flag|
|0||ACKF||Acknowledgement level flag|
Of these fields, only DRF supports write operations, this being set when data in the data register (DR) is ready for sending.
When a byte has been transferred from the data register, DRF is then cleared, and this condition should be used to prepare another byte for transfer.
When reading data, DRF is cleared and subsequently tested. When a byte has been transferred to the data register, DRF is set, and this condition should be used to obtain the transferred data and to prepare to receive any further bytes from the bus.
The acknowledgement level flag (ACKF) reflects the bus signal level indicating acknowledgement (ACK) or non-acknowledgement (NACK). Here, a low level indicates an acknowledgement condition (ACK), and a high level indicates non-acknowledgement (NACK).
The clock generator register (GR) is arranged as follows:
|15..0||Clock divider (encoded)|
Apparently, the appropriate formula is...
I2C frequency = Device clock frequency / (Clock divider * 16)
Clock divider = Device clock frequency / (I2C frequency * 16)
The GR field is populated with an encoded value of the divider minus one, with zero therefore encoding a divider of one.
Thus, to use an I2C frequency of 400kHz, the following calculation would be used:
Clock divider = Device clock frequency / (400000 * 16)
To attain the appropriate I2C frequency, the device clock (pclock, PCLK) needs to be configured appropriately, multiplying the input clock if necessary.
In modern kernels, the following files are pertinent: