Table of Content
The memory map of the SoC (particularly the peripheral memory)
Memory Map
The JZ4730 has a memory map with the following principal regions of interest:
| Start Address | End Address | Size | Function |
|---|---|---|---|
| 0x00000000 | 0x07FFFFFF | 128MB | SDRAM |
| 0x08000000 | 0x0FFFFFFF | 128MB | Static memory |
| 0x10000000 | 0x10FFFFFF | 16MB | APB I/O devices |
| 0x11000000 | 0x12FFFFFF | 32MB | (Reserved) |
| 0x13000000 | 0x13FFFFFF | 16MB | AHB I/O devices |
| 0x14000000 | 0x1FFFFFFF | 192MB | Static memory |
| 0x20000000 | 0xBFFFFFFF | 2GB | SDRAM |
| 0xC0000000 | 0xCFFFFFFF | 256MB | PC card socket 0 memory |
| 0xD0000000 | 0xDFFFFFFF | 256MB | PC card socket 1 memory |
| 0xE0000000 | 0xFFFFFFFF | 512MB | (Reserved) |
(The 2GB region from 0x20000000 is actually pertinent on the MIPS Creator CI20 which provides 1GB RAM, but where the region from 0x00000000 has only been upgraded to provide access to 256MB RAM.)
The I/O or peripheral memory is described below.
I/O Memory
The JZ4730 offers the following regions for configuration of and interaction with peripherals:
| Start Address | End Address | Peripheral |
|---|---|---|
| 0x10000000 | 0x10000FFF | CPM (clock and power management, see Clocks) |
| 0x10001000 | 0x10001FFF | INTC (interrupt controller) |
| 0x10002000 | 0x10002FFF | OST (operating system timer, see Clocks) |
| 0x10003000 | 0x10003FFF | RTC (real-time clock) |
| 0x10004000 | 0x10004FFF | WDT (watchdog timer, see Clocks) |
| 0x10005000 | 0x1000FFFF | (Reserved) |
| 0x10010000 | 0x10010FFF | GPIO (general purpose input/output) |
| 0x10011000 | 0x1001FFFF | (Reserved) |
| 0x10020000 | 0x10020FFF | AIC (AC97/I2S controller, audio) |
| 0x10021000 | 0x10021FFF | MSC (MMC/SD controller, memory card) |
| 0x10022000 | 0x1002FFFF | (Reserved) |
| 0x10030000 | 0x10030FFF | UART0 (UART #0) |
| 0x10031000 | 0x10031FFF | UART1 (UART #1) |
| 0x10032000 | 0x10032FFF | UART2 (UART #2) |
| 0x10033000 | 0x10033FFF | UART3 (UART #3) |
| 0x10034000 | 0x1003FFFF | (Reserved) |
| 0x10040000 | 0x10040FFF | FIR (fast infrared port) |
| 0x10041000 | 0x10041FFF | SCC0 (smartcard controller 0) |
| 0x10042000 | 0x10042FFF | I2C (inter-integrated circuit bus) |
| 0x10043000 | 0x10043FFF | SSI (synchronous serial interface, SPI) |
| 0x10044000 | 0x10044FFF | SCC1 (smartcard controller 1) |
| 0x10045000 | 0x1004FFFF | (Reserved) |
| 0x10050000 | 0x10050FFF | PWM0 (pulse width modulation, PWM) |
| 0x10051000 | 0x10051FFF | PWM1 (pulse width modulation, PWM) |
| 0x10052000 | 0x1005FFFF | (Reserved) |
| 0x10060000 | 0x10060FFF | DES (data encryption standard) |
| 0x10061000 | 0x10061FFF | UPRT (micro printer controller) |
| 0x10062000 | 0x10062FFF | KBC (PS/2 keyboard controller) |
| 0x10063000 | 0x10FFFFFF | (Reserved) |
Note that the DES peripheral is omitted from documentation but mentioned in the legacy kernel source code.
| Start Address | End Address | Peripheral |
|---|---|---|
| 0x13000000 | 0x1300FFFF | HARB (AHB bus arbitration) |
| 0x13010000 | 0x1301FFFF | EMC (external memory controller) |
| 0x13020000 | 0x1302FFFF | DMAC (DMA controller) |
| 0x13030000 | 0x1303FFFF | UHC (USB host controller) |
| 0x13040000 | 0x1304FFFF | UDC (USB device controller) |
| 0x13050000 | 0x1305FFFF | LCD (LCD controller) |
| 0x13060000 | 0x1306FFFF | CIM (camera interface module) |
| 0x13070000 | 0x130FFFFF | (Reserved) |
| 0x13100000 | 0x1310FFFF | ETH (Ethernet MAC controller) |
| 0x13110000 | 0x13EFFFFF | (Reserved) |
| 0x13F00000 | 0x13F0FFFF | NBM (NAND flash boot module) |
| 0x13F10000 | 0x13FFFFFF | (Reserved) |